SU1642589A1 - Threshold decoder of any system code - Google Patents

Abstract

The invention relates to computing and communication technology. Its use in computer networks and communication channels of discrete information transmission systems increases noise immunity. The threshold decoder contains a syndrome driver 1, a test driver 2, a data register 3, switches 4-6, a test analyzer 11, a comparison block 13, a modulator 16 16 and a control block 17. Due to the introduction of the switch 7, the register 8 of symbol reliability, the minimum selection block 9, the check reliability register 10, the subtraction block 12 and the comparison blocks 14, 15, soft decode is performed at the decoder without introducing errors to the correct position. 4 hp f-ly, 6 ill. in 44M SL C

Description

20 121

1

The invention relates to computing technology and communication technology and can be used in computer networks and communication channels of discrete information transmission systems, on the internal stage of which multiposition signals are used.

The purpose of the invention is to improve noise immunity.

1 shows a block diagram of a decoder; figure 2 - block diagram of the analyzer checks; Fig. 3 is a block diagram of a control unit; Fig, 4 is a block diagram of a shaper syndrome; figure 5 is a block diagram of the minimum selection block; Figure 6 shows signal timing patterns explaining the operation of the decoder.

The q-ary code threshold decoder contains shaper 1 syndrome, shaper 2 checks, data register 3, first to fourth switches 4-7, symbol reliability register 8, minimum selection block 9, test reliability register 10, check analyzer 11, subtraction unit 12, the first to third comparison blocks 13-15, the adder 16 modulo q and the control block 17. In FIG. 1, the first 18 and second 19 information inputs, the clock input 20 and the synchronization input 21 are indicated.

The check analyzer 11 for the case of four input symbols contains (FIG. 2) a unit 22 for calculating the sum of reliability of the same symbols, a decoding unit for decoding zero symbols, a maximum selection block 24, a switch group 25, first-third multiplexers 26-28, and a group of 29 comparison elements. Figure 2 marked the first 30 and second 31 inputs and the first to fourth outputs 32-35.

The unit 22 for calculating the sum of reliability of the same symbols included in the analyzer 11 (Fig. 2) multiplexers 36, binary counters 37, comparison elements 38, adders 39 and I elements 40.

Block 23 decoding of zero characters, also included in the analyzer 11, is made (Fig, 2) on the decoder 41 zero and the elements And 42.

The control unit 17 contains (FIG. 3) the first to fourth binary counters 43-46, the first-third sources 47-49 of a constant code, and a frequency divider 50. FIG. 3 denotes synchronization input 51, clock input 52, first-fifth exits 53-57.

Shaper 1 syndrome is made in accordance with the code used (Fig, 4) on registers 58-61. switches 62 and 63 and adder 64 modulo q.

Register 8 reliability of the characters is the same as the shaper 1 syndrome, with the exception of the adder 64 modulo q, and the outputs of the registers 58-61 are connected to block 9.

The check generator 2 is implemented in accordance with the check matrix of the selected code on the adders modulo q.

The minimum selection block 9 contains (FIG. 5), for example, comparison elements 65-67 and multiplexers 68 and 69.

The maximum selection unit 24 included in the analyzer 11 is configured in the same way as block 9, but more than the outputs are used in the comparison elements 65-67.

Sources 47-49 of the constant code of block 17 form codes, the values of which are indicated below.

In fig.b, the following signals are designated in control block 17: a - pulses

synchronization; b - clock pulses; c - pulses at the output of the frequency divider 50; g - signal at the second output 54 (the first output of the counter 43); d - signal for installation of counters 44-46 (from the last output of the counter43).

The decoding algorithm of the q-ary majority code using the reliability of the symbols is as follows. We have (n, c, 5) h-code, where n is the code length; k

- the number of information characters; S is the number of checks; V is the minimum code distance; q - the significance of the code. Let "1, QZ, ..., On be the values of the received code symbols; , fofin - reliability of the received symbols, moreover, at {0,1 ..., g -1}, and

/ ft Ј {0.12W}, where W is the multiplicity of inputs

19, in general, / g Ј {0, I. 2II (2W - 1)},

where I is a whole. All code symbols are decoded sequentially. When decoding

The f-ro character is calculated by the cp (f 1, n; p 1,5} p-value and check for the f-ro character. Each test Qfn is assigned all ytn equal to the minimum reliability of the character entering it

(f rn;, o). Next, we calculate the values of At and AO:

At 2 y (priO From), t Ј {1, S}; AO 2) (with Qt 0), t Ј- {1, S};

those. the sum of the reliability of the checks, the hard value of which is equal to Qt, and the sum of the reliability of the checks, the hard value of which is zero. Then we find the values

fan - At - ---, the maximum of which

compare with the threshold, and the corresponding / up & 0, the value of t is compared with the threshold T. If the value of 0 exceeds the threshold / and the corresponding value of t over threshold 1, we assume that the error value is equal to Qt. Then ttf (at - Of) mod q. If any of the specified thresholds are not exceeded, the correction does not occur and. Next, the decoding of the next character is performed.

Taking into account the above algorithm, the threshold decoder works as follows.

The information arriving at the inputs 18, which is the word of the q-ary majority (n, k, y) code, is written to the syndrome former 1 and through the first switch 4 to the data register 3. The switch 4 is in a position that provides for recording k information symbols from a sequence of length n. Simultaneously, the reliability register of symbols from inputs 19 are written to the reliability values of code symbols. After the end of the recording, the process of forming the syndrome begins. At the same time, the code word symbols are promoted along the register of the syndrome former 1 and from the corresponding taps are fed to the adder 64 modulo q. At the same time, the numbers corresponding to the reliability of the characters are promoted across the register of character reliability 8.

In the formation of each symbol of the syndrome involved several code symbols (in accordance with the properties of the code). At the same time, the inputs of the minimum selection block 9 receive values corresponding to the reliability of each of the code symbols involved in the formation of this syndrome symbol. In accordance with the above algorithm, this symbol of the syndrome will correspond to the minimum reliability of the reliability of the code symbols included in it (the syndrome). Each syndrome symbol is sequentially recorded in the shaper 2 checks, at the same time the corresponding reliability value is recorded in the check reliability register 10. The outputs of blocks 2 and 10 are connected to the analyzer 11. In this case, the outputs of the driver 2 and register 10 are selected in accordance with the code properties (for example, for a self-orthogonal quasi-cyclic code (32, 26) these are taps 1, 2, 5, and 1, 3, 8 ). From register 10 to the inputs of analyzer 11, the values of the corresponding reliability checks are received.

The analyzer 11 is designed to form the following values: the sum of the reliability of the checks, the hard value of which is zero; maximum of sums

the reliability of checks whose hard value is equal to Qt; the number of checks that have the same Qt value and have the maximum amount of reliability; values of checks that are the same

0 value and having the maximum amount of reliability.

The analyzer 11 operates as follows.

 To the inputs 30 of the sum calculation unit 22

5 of the reliability of the same symbols, the values of the symbols Si, ..., Sn are received from the outputs of the driver 2 checks, and the inputs 31 are given the corresponding values of reliability Pi Pn from the outputs of the register 10 reliability checks. In comparison elements 38, a pair-wise comparison is made between the incoming values of the checks among themselves for the detection of identical values. The signals from the outputs of the comparison elements 38 control the multiplexer 36, which, using these signals, passes the corresponding reliability value to the inputs of the adders 39 (if there are no identical symbols, all four

0 adder 39). In addition, counters 37 accumulate information about the number of identical among the input symbols. At the same time, in block 23 of decoding zero characters, the presence of

5 null characters among input. The code sequence formed by the outputs of the decoders 41 zero of the unit 23 controls the switches 25 passing the sum to the maximum selection unit 24

0 reliability of symbols with the same non-zero value (first outputs 32), as well as multiplexer 26, the outputs of which receive the sum of reliability checks, the hard value of which is zero (even 5 outputs 35). Further, the reliability of the symbols having the same value is compared in the elements 29 with maximum reliability and the resulting code controls the multiplexer 27, from which

0 second outputs 33 receives the value of the number of checks that have the same value and have maximum reliability. The same code controls the next multiplexer 28 and passes to the third ones

5 outputs 34 values of the number of checks that received the same value.

After the indicated values are formed at the outputs of the analyzer 11 in the second comparison unit 14, a comparison is made with the zero threshold formed in the control unit 17 to the difference between the maximum of the sums of reliability. checks, the hard value of which is equal to Qt, and the sum of the reliability of the checks, the hard value of which is zero. The threshold exceeding signal opens the second switch 5 and to the inputs of the first comparison unit 13 receives the maximum of the sum of reliability tests, the hard value of which is equal to Qt. If this threshold is exceeded, the excess signal opens the third switch 6 and a third value is supplied to the inputs of the third comparison unit 15, formed in the analyzer 11. Exceeding the threshold allows the Qt value to go to the inputs of the adder 16. which is the error value. The other inputs of the adder 16 comes from the register 3 of the data value of the erroneous character ad. In this case, the value of the corrected symbol a; (od - qf) mod q.

In a threshold decoder, two thresholds are set based on the probability of a symbol (reliability), one of which is zero, and according to the number of checks that have the same value. This makes it possible not to introduce errors in the correct position.

The threshold decoder takes into account the maximum likelihood decoder by taking into account the reliability of the symbols. The use of a soft solution allows to significantly improve the decoding results. This scheme is especially effective in a channel with -variable parameters.

Claims (5)

1. The threshold decoder of the q-ary code containing the syndrome generator, the information inputs of which are combined with the corresponding information passages of the first switch and are the first information inputs of the decoder, the outputs of the syndrome generator and the first switch are connected to the inputs of the verification generator and the data register, respectively. the outputs of which are connected to the first inputs, respectively, of the test analyzer and the modulo q adder, whose outputs are decoder outputs, the first and second outputs analysis The checks are connected to the information inputs of the second and third switches, respectively, the outputs of the second switch are connected to the first inputs of the first comparator unit, the control unit, the clock input and the synchronization input of which are of the same name the decoder inputs, the first output of the control unit is connected to the control input of the first switch and the first control input of the syndrome generator, the second output of the control unit is connected to the second control input of the syndrome generator, the third outputs of the control unit are connected to the second inputs of the first comparison unit, the output of which is connected with a control input of the third switch, characterized in that, in order to improve noise immunity, a minimum selection unit, a subtraction unit, a fourth switch, a second The first and third blocks of comparison, the register of reliability of checks and the register of reliability of symbols, the information inputs of which are the second information inputs of the decoder, the first and second control inputs of the register of reliability of symbols are connected respectively to the first and second inputs of the control block, the outputs of the register of reliability of symbols are connected with the inputs of the minimum selection block, the outputs of which are connected to the inputs of the check reliability register, the outputs of which are connected to the second inputs of the check analyzer, third and fourth The rotary outputs of which are connected respectively to the information inputs of the fourth switch and the first inputs of the subtraction unit, the second inputs of which are connected to the first outputs of the check analyzer, the outputs of the subtraction unit and the fourth outputs of the control unit are connected to the first and second inputs of the second cp-avnogo unit, the output of which is connected to the control input of the second switch, the outputs of the third switch and the fifth outputs of the control unit are connected to the first and second inputs of the third comparison unit, the output of which is connected chen to the control input of the fourth switch, the outputs of which are connected to the inputs of the adder Stora modulo q, 2. The decoder according to claim 1, wherein the test analyzer comprises a decryption block of zero symbols, a maximum selection block, first to third multiplexers, a group of switches, a group of comparison elements and a block for calculating the sum of reliability of the same symbols, the first inputs of which are combined with the corresponding inputs the null character decoding unit and the information inputs of the third multiplexer and are the first inputs of the analyzer, the second inputs of the unit for calculating the sum of reliability of the same symbols are the second input E analyzer, the first unit outputs calculating the sum of reliabilities of the same symbols is connected to the information inputs of the corresponding switches of the group, to the first inputs of the corresponding elements of the group comparison and to the corresponding information inputs of the first multiplexer, the outputs of the decoding block of zero symbols are connected to the corresponding address inputs of the first multiplexer and the control inputs of the corresponding switches of the group whose outputs connected to the corresponding inputs of the highlight unit, the outputs of which are connected to the second The inputs of all elements of the comparison group are the first outputs of the analyzer, the second outputs of the sum of reliability unit for calculating the same characters are connected to the corresponding information inputs of the second multiplexer, the outputs of the comparison elements of the group are connected to the corresponding address inputs of the second and third multiplexers, the outputs of which are the outputs of the first multiplexer respectively the second and fourth outputs of the analyzer. 3. The decoder according to claim 2, characterized in that the block for calculating the sum of reliability of the same symbols contains h multiplexers (h is the number of groups in the first and second inputs of the verification analyzer), h binary counters, h adders, b-2 elements And and Ch2 elements comparison, the first and second inputs of each of which are connected to the corresponding pair of groups of the first block, i.e. the information inputs (I 1, h) of the first - 1st multiplexers are connected to the i-th group of the second inputs of the block, the outputs of the comparison elements, the first inputs of which are connected to the i-th group of the first entrances block, connected to the corresponding address inputs of the 1st multiplexer and counting inputs of the i-ro binary counter, the outputs of the comparison elements, the second inputs of which are connected to the i-th (except ih) group of the first inputs of the block, are connected to the inputs of the corresponding element And whose output connected to the control inputs ix of the multiplexer and the binary counter, the output of the comparison element whose inputs are connected to a pair of the last groups of the first block inputs, connected to direct address inputs (n-1) -x and inverse address inputs of h-x multiplexers and binary counters, multiplexer outputs connected to inputs of the same adders, whose outputs and binary counter outputs are, respectively, the first and second outputs of the block, 4. The decoder according to claim 2, characterized in that the decoding block of null symbols contains h decoders zero and h-2 elements, And the first inputs of the first h-ro decoders zero are the corresponding inputs of the block, the output of the first decoder zero is connected to the second input The second decoder is zero and the first one of all AND elements is the first bit of the block outputs, the Ko output of the decoder zero (j 2, h-1) is connected to the j-th inputs (J-1} - th - (h-2) - The ro elements of AND are the jth bit of the outputs of the block, the output of the h -ro decoder zero is the hth digit of the outputs of the block. 5. The decoder according to claim 1, wherein the control unit contains the first-fourth binary counters, the first to third sources of a fixed code and the frequency divider whose clock input is the clock input of the block, the zero zero inputs of the frequency divider and the first binary counter are combined and are the synchronization input of the block, the output of the frequency divider is connected to the counting inputs of all binary counters and is the first output of the block, the first output of the binary counter is the second output of the block, the last output of the first binary counter ka is connected to its control input and the reset input of the second to fourth binary counters, the outputs of the first to third DC source code with adjusting inputs are connected, respectively, the second to fourth binary counters, the outputs of which are respectively third n-tymi block outputs. one t "M -t Mj Hesfes Ј -. tabd 1z -t- O4 HF5-.   gcha. ta fcdfcdta ed   . . i -OjfS -fi Oj IN. V b) tatdta I S-U4 "V - H t- a -Jw five h & h  Record information formation of the syndrome Decoding PP characters 1 g K / f + 2 . dmtn 2 / f J / r ..P P.