SU1642462A1 - Device for data search - Google Patents

Abstract

The invention relates to computing and can be used to read and select from an information data file, necessary, for example, in an automated vocabulary learning system. The purpose of the invention is the extension of functionality — due to finding a record with a given search key and maximum priority. The goal is achieved by the fact that the device contains the first and second counters 1 and 2, the decoder 3, memory block 4, first register 5, register key key 6, register 5 priority field 7, register 5 data field 8, search sign input 9 devices, the first comparison node 10, the first 15, the second 16 and the third 17 elements And, the 18-clock pulse generator, the first and second delay elements 19 and 20, and the second register 21. 1 or 0 with S (L oe N5 OE s

Description

The invention relates to computing and can be used to read and select from an information data set, for example, required in an automated vocabulary learning system. The purpose of the invention is to expand the functionality by finding a record with a given search key and maximum priority.

The drawing shows a diagram of the proposed device.

The device contains the first and second counters 1 and 2, the decoder 3, the memory block 4, the first register 5, register register key 5 6, register 5 priority field 7, register 5 data field 8, device search sign input 9, first comparison node 10 , outputs of the inequality flag 11 and the equality sign 12 of the comparison node 10, priority register 13, second comparison node 14, first 15, second 16 and third 17 And elements, clock generator 18, first and second delay elements 19 and 20, second register 21 , device start input 22, information input 23 (devices, output 24 characteristic finality | no work and exit 25 result tron devices.

 The device works as follows.

Information retrieval is initiated by applying a pulse to input 22, as a result of which a clock pulse generator 18 is triggered. The first pulse from its output is the reception of the initial record in the register 5 ". Further, depending on the ratio between the key of the desired record and the record key located in register 5, the device can work in two ways.

In the case when the key of the read record does not coincide with the key of the desired record, the signal at output 11 of node 10 appears, preparing the element AND t60 for actuation. When a pulse appears at the output of the decelerating element 19, the element 16 triggers, resulting in a pulse the counting input of counter 1 and its contents increase by one. The second pulse from the generator output of 18j pulse pulses in accordance with the address recorded in the counter 1, the register 5 receives information

0

five

0

five

0

.p 35

40

45

55

from memory block 4, the key of which is analyzed in the same way

In the case when the key of the read record matches the key of the desired record, a signal appears at output 12 of node 10, preparing element 15 for triggering. When a pulse appears at the output of delay element 19, element 15 triggers. At the counting input of counter 2 and a pulse arrives at the synchronization input of node 14, as a result of which the contents of counter 2 are increased by one and the operation of node 14 of comparison is allowed

If the contents of register 7 priority register 5 are greater than the contents of register 13, then the output of node 14 is a signal that prepares element 17 for triggering. When a pulse appears at the output of delay element 20, element 17 activates, resulting in the contents of field 7 of priority Register 5 is rewritten into register 13, and the contents of data field 8 are entered into register 210.

In the future, the device works similarly.

I

When iterating through all the addresses determined by the contents of counters 1 and 2, a signal appears at the overflow output of counter 2, through which the counters 1 and 2 and register 13 are reset, and the clock pulse generator 18 stops. At the same time, the output of the device 24 is signaled about the end of the search process, in the register 21 there is a search record (data field) with the specified search key and the maximum priority that goes to the output 25 of the device

Claims (1)

Invention Formula A device for searching information, comprising a first counter, a decoder, a memory unit, a first register, a first comparison node, a first AND element, a first delay element, and a clock generator, with the device start input connected to the clock generator start input Pulses whose output is connected to the write-read input of the first register and the input of the first delay element whose output is connected to the first input of the first element AND, the output of the memory unit is connected to the information input of the first register whose first output is connected to and the output of which is connected respectively to the output of the inequality sign of the first comparison node, and the counting input of the first counter, the output of the first element I is connected to the synchronization input of the second comparison node and the counting input of the second counter, whose information outputs are below the first information input of the first switch to the inputs of the second group of the descramble comparison, the output of the equalizer flag, the output of the overflow of the second which is connected to the second meter connected to the installation input the input of the first element is And, the input is a prize-in About the first counter, the input of the device search unit is connected to the keys in the About priority register, the second information entry of the first | clock generator stop input Comparison node, characterized in that, in order to expand its functionality by finding a record with a given search key and maximum priority, it contains a second counter, a second register, a priority register, a second comparison node, a second delay element, a second and third And elements, the information input of the devices is connected to the information input of the first counter, the information outputs of which are connected to the inputs of the first group of the decoder, the outputs of which are connected to the address inputs of the memory block, output n The first delay element is connected to the input of the second delay element and the first input of the second element, And the second input pulses and output of the end of work, the output of the second delay element is connected to the first input of the third And element, the output of which is connected to the write-read inputs of the second register and the priority the first start of the information input of the second comparison node, the output of which is connected to the second input of the third element, the second output of the first register is connected to the information input of the priority register and the second information input of the second comparison node, the third output of the first register is connected to the information input of the second register, the output of which is connected to output result of the device.