SU1635220A1 - Buffer memory - Google Patents

Description

(21) 4651414/24

(22) 13.02.89

(46) 03/15/91. Bul № 10 (72) V.G.Okolotenko, A.A. Shcherbak, V.G.Fyodorov, I.D.Shulgina, A.G. Bondarenko and S.F.Muteremov

(53) 681.327.6 (088.8)

(56) USSR Author's Certificate No. 651412, cl. G 11 C 19/00, 1977.

USSR Author's Certificate No. 1241288, cl. G 11 C 19/00, 1984.

(54) BUFFER STORAGE DEVICE

(57) The invention relates to computing and can be used in the construction of buffer storage devices in data transmission and reception systems, for example, as input buffer registers. The purpose of the invention is to increase reliability. The device contains a group of elements AND 1, register 2, a multi-input element OR NONE 3, D-flip-flop 7. Introduction to the generator device 5 pulses with an external trigger, a pulse counter 4 and a decoder 6 allows us to distinguish useful information from false and significantly increase the reliability of the device. 1 il.

The invention relates to computing and can be used in data transmission and reception systems, for example, as input buffer registers.

The aim of the invention is to increase the reliability of the device.

Diagram of the device shown in the drawing.

The buffer memory contains a group of elements AND 1, the outputs of which are connected to the corresponding inputs of register 2. The output of the multi-input element OR-NOT 3 is connected to the embedding input of the counter of 4 pulses, the start input of the generator of 5 pulses. The clock input of the counter of 4 pulses is connected to the output of the generator of 5 pulses, the bit outputs of the counter of 4 pulses (except the oldest one) are connected to the inputs of the decryption-. rator 6. The output of the decoder 6 is connected to the installation input to the unit state of D-flip-flop 7, the clock input of which is connected to the high-order output of counter 4, the D-input of the trigger 7 is connected to the output of the element OR NOT 3. The information inputs 8 of the device are connected to the inputs of the element OR-NOT and to the first inputs of the elements AND of the group, the second inputs of which are connected to the output of the D-flip-flop.

The device works as follows.

Before starting operation, D-trigger 7 is zeroed (zeroing chains are conventionally not shown). The group of elements And 1 is blocked by a low level signal

from the direct output of the D-flip-flop 7. At the output of the decoder 6 in the initial state there is a signal of a low logic level.

The information inputs 8 in the absence of a signal also have low logic levels, so the output of the OR-NOT element in the initial state is a high logic level signal, blocking the counter of 4 pulses on the return terminal and the generator of 5 pulses on the trigger input, thereby generating no impulses occur.

The input code in the form of pulses of a unit level of a certain duration simultaneously arrives at the first inputs of the group of elements AND 1 and the inputs of the multi-input element OR NONE 3. Since at least in one bit of the input code combination there is a single level, at the output of the element OR NI 3 the operating time of the useful signal is set to a low logic level, which triggers the generator of 5 pulses and unlocks the counter of 4 pulses at the roundabout input. Counter 4 is filled with pulses coming from the output of the generator 5 to its clock input. When the counter reaches 4 pulses of a predetermined state (in time, this corresponds to a moment approximately equal to half the duration of the input pulses), the decoder 6 is triggered, setting the D flip-flop 7 to a single state by a high logic level signal. The high logic level signal from the output of the D-flip-flop 7 unlocks the group of elements AND 1 by the second inputs, which pass the input code combination from the information inputs 8 of the device to the corresponding inputs of the register 2. At the same time, the corresponding bits of the register 2 are set to one, t. e. information is recorded. When the counter reaches 4 pulses of such a state, when a high logic level signal appears at the high-order output, the D-flip-flop 7 is set to the zero state, because its D-input has a level O from the output of the OR-HE 3 element ( Code package is not over yet). Switching, D-, trigger 7 blocks on the second inputs

0

five

with

Q 5

thirty

35

40

45

50

55

a group of elements And 1, so that the recording stops.

A further change in the logic levels at the information inputs 8 of the device does not affect the state of register 2.

The minimum time interval between the operation of the decoder 6 and the switching to the zero state of the D flip-flop 7 is determined by the time required for reliable recording of the input information in register 2, the maximum one by the duration of the code pulse.

When an impulse noise device arrives at information input 8, the duration of which is significantly less than the duration of the code pulse, false information is not recorded in register 2, since during the time of the effect it does not have enough time to fill the counter of 4 pulses, therefore, the decoder would not work and D- trigger 7 will not open a group of elements AND 1. After the interruption of the interference by a high logic level signal from the output of the element OR NOT 3, the counter of 4 pulses is zeroed, the generator 5 is blocked by the input of the external launch, i.e. the device returns to its original state.

As a pulse counter 4, binary counters of the corresponding chip series can be used, the width of which is determined by the duration of the incoming code pulses and the frequency of the generator 5. For example, if the length of the code pulse is 8-10 times longer than the period generated by the generator 5, One binary counter (for example, 155IE5, 564IE10, etc.).

The decoder 6 for the above example can be implemented, for example, on element 2I, to the inputs of which signals are output from the first and third bits of counter 4. The output of the senior (fourth) digit of the counter must be connected to the clock input of the D-flip-flop.

The frequency to which the oscillator 5 is tuned is determined by the length of the code premises and the duration of possible interference from the communication lines to the information inputs of the device.

Thus, the invention allows to differentiate useful and false information, which significantly increases the reliability of the buffer storage device.

Claims (1)

Claims A buffer storage device containing a register, the inputs of which are connected to the outputs of elements AND groups, the first inputs of which are information inputs of the device, the element OR NOT and a trigger, the output of which is connected to the second inputs of elements AND of the group, characterized in that , in order to increase the reliability of the device, a pulse counter, a decoder and a pulse generator are inputted into it, the output of which is connected to the clock input of the pulse counter, the output terminal of which is connected to the output of the OR-NOT element, the trigger input of the pulse generator and the D-input of the trigger; the bit outputs, besides the high pulse counter, are connected to the inputs of the decoder, the output of which is connected to the trigger setup input, the clock input of which is connected to the high pulse pulse output inputs of the element OR NOT connected to the first inputs of the element AND group.