SU1615706A1 - Multiplying device - Google Patents

Abstract

The invention relates to digital computing and can be used in high-performance machines and systems. The aim of the invention is to increase the speed by introducing two registers, two switches, two adders and corresponding connections. The device operates according to the conveyor principle, due to the presence of partial product registers in it, and each cycle is multiplied by the next P bits of the higher and lower multipliers, (where P * 983), and in the process of multiplying the simple main equipment is reduced to the minimum. 3 il.

Description

The invention relates to digital computing, is intended to multiply the numbers represented in the binary number system, and can be used as an operation unit in high-performance computing machines and systems.

The aim of the invention is to increase speed.

In the device operands are positive numbers, represented as

A 21a; 2, a; 6fo, l, where a

... the binary p-bit code of the number A. The execution of the multiplication operation in the device is based on the tabular-algorithmic multiplication method using pipelining by combining in time the production of elementary products

l

U..2 is the accumulation of partial products and parallelization by combining in time the calculation of the products of the multiplicand by the upper and lower parts of the multiplier.

tt

Let X x - 2 and Y

multiplier and multiplier respectively, where X; and y are the values of the i-x bits of the multiplier codes. Then, a 2n-bit binary code is required to represent the exact result of Zx "Y.

The process of calculating works

Z is written in the form l

Z z: (Y: z: x, - (). (2g, (1) -I

where is x

X; x

 1 + 1

 to

, Chr-1 is a binary-coded digit of the code of the multiplicand in a caus

but

SP

positional number system with base q

  y; yj4.f -yj + p-i is a binary-coded cylinder of the multiplier code.

If Y is presented as the sum of the older and younger parts:

ABOUT

2

IL

where; the process of calculating Z

(2) will be recorded

view if

 Z

,

J., RFCx: (2)). (+

(Y

(2V) .2 r

(3)

Thus, the multiplication process consists of repetitive cycles of the same type. During the next j-ro cycle, the jth partial product of Y p.cr.j

 D- X; 2 multiplicands on the next

bits of the highest part of the multiplier

  n is calculated by K multipliers,

P

on

R

thirty

performing the multiplication operation of the p-times of the binary binary code Y: by the p-fold of the binary code X, with the formation of a product of 2p. Then the elementary products are assembled into the n + p binary-bit code of the partial products of YCT. J on the 35 adder, at the same time on the same K multipliers, elementary products of X are formed by successive rains of the younger part of the multiplier Y, which are then assembled into partial production on another adder.

The presence of partial product registers with appropriate control allows organizing a pipeline to calculate X or X-Yd, d, when at the same time a partial product X YpT.jV, MAji-i is formed on the corresponding adder and on the other adder the sum of the parts "-O

40

45

50

ZJ..T.J X YCT.J (or Z

+ + X Y

md one

ssy or X

 ZCT.I .. --i7 9-P

Zw, j., 2

+

+

YMA. () Calculation Processes

 cT.j-n WA.j are shifted in time.

MA.

R

and Z

ct.J

55

After calculating --- n-bit

ten

15

0

five

0

five

0

five

0

five

Z - Zj is summed on one of the adders of Z- and n most significant bits of Z. As a result

3

are determined --- n high order bits

Z, and the lower - | - bits are defined when calculating Z ,,.

Figure 1 shows the functional diagram of the multiplier; figure 2 is a relative time scan of the signals at the outputs of the synchronization unit; on fig.Z - an example of the implementation of the synchronization unit.

The device (figure 1) contains the registers of multiplicable 1 and the younger part of the multiplier 2, K multipliers 3 - 3 ,, the second adder 4 elementary works, the second adder 5 partial works, block 6 synchronization, register 7 older parts of the multiplier, the first switch 8, the first adder 9 elementary products, the first 10 and second 11 registers of partial products, the second switch 12, the first adder 13 partial products, registers older 14 and younger 15 parts of the result.

Synchronization unit 6 (FIG. 3) contains outputs 16-21, start input 22, clock input 23, RS flip-flop 24, AND 25, counter 26 and memory element 27.

Register 1 of the multiplier is intended to store the multiplicand.

x i: x; (2 r Хх, .. (2) -.

Register 7 of the higher part of the multiplier. Shift, bit, and

the shift is carried out by a number of bits, intended for storage Y.

The multipliers 3 - 3 | (designed to calculate the next elementary product X; -Yj, i, .., ..., K, have two p-bit inputs and a 2p-bit output. As multipliers, one can use clock matrix multipliers or ROMs with a stitched multiplication table in a 2-number system.

The first switch 8 - p-bit d-ny, is designed to transmit to the input multipliers corresponding to the p bits from register 7 or 2.

Register 2 M) 1 part multiply

Z values. and Z ddd

to determine l - - | - + p-bit dny, shear.

moreover, the shift is carried out by a number of orders, intended for storage

ALA The first and second adders of 4 and 9 elementary products, n-bit, are designed to form the higher n bits of the partial products of Y, X, and Y ,. X respectively.

The first and second registers P and 10 partial products, n p-Parse, are intended for storing partial products YJ, q X and YfT-GC, respectively, n bits of which are received: from the corresponding adder 4 and 9, and younger bits are from multiplier 3 ,.

The second switch 12 is designed to transmit to the input of the second term of the adder 13 partial products of the operand from the register of 10 partial products or higher n bits of the register 15 lower part of the result.

The adder of 5 partial products - two-input, pz-p-bit dnsh, is designed to calculate the value of-.

The adder 13 partial products - 3 research institutes - two-input, --- n-bit,

designed to calculate the values of Zp-r j and the sum of Z Z f-f +.

Register 14 of the highest part of the product

The day is --- n + p-bit dny, shear, and the shift is made by p-bits. Register 15 | - n + p-bit, shift, and the shift is carried out by p bits.

The synchronization unit 6 provides for the formation of control signal sequences (FIG. 2),

The device operates as follows.

3 of the initial state in register 1 is the multiplicand X, in the higher bits of register 2 - the younger part of the multiplier Uddd, in register ee 7 - the highest part of the multiplier YC, -, registers 10, 11 14 and 15 are cleared (in Fig. 1 reset and power not shown).

In each cycle, the signal at outputs 19, 21, and 17 of the synchronization block is followed by the formation of K elementary products, i 1, ..., K, the content shift registers 157066

ra 2 in the direction of the lower bits in the ra bits, the addition of the elementary products formed on the previous (-1) cycle on the adder 4 and behind - | writing the result to register 11, adding the partial product X formed in (jl) -M cycle, -Yj.7-: - 1 with the contents of register 14 on summator 13 (cr j-rl add zeros), shifting the contents of register 15 into to the range of low-order bits for p-bits. Further, the signals at the outputs 18, 19 and 16 of the synchronization unit occur

j formation of K elementary products shift of the contents of register 7 towards the lower-order bits by p bits, the addition of the previously formed X; YpT j, i 1К by

20 adder 9 and write the received XYpf to register 10, add the contents of register 11 with the contents of register 15 on adder 5 and write the result to register 15 (for j 1

25 add up zeros), shifting the contents of the register 14 to the side of the lower bits to a number of bits. one

n to

After 2 cycles of multiplication, the addition of the contents of register 10 with the contents of register 14 on the output of the synchronization unit 21 takes place on the adder 13 and the recorded upper part of the product Z, is recorded. 3i per register 14. For the same signal, an addition occurs on the adder of 4 forms K

mirovannyh in the latter (j --.-)

the elementary product cycle .j, the recording of the formed partial product XYd to registrar 11. Next, the synchronization block output 16 output signal, the addition of the contents 45 of registers 11 and 15 on the adder 5 and the younger part of the product Z is written to register 15. To signals at the outputs of the 20 and 21 block sync. zation occurs addition on the sum- 50 3

torus 5 n-bit code n

 senior bits Z d obtained

. 3 values --- n bits Z recorded

55 per register 14, and the lower order bits Z are in the lower order bits Z are in the lower register bits 15.

71615706

formula of invention

n m with n in 2Q and ix with

j A device for multiplying, containing; the multiplier register, the registers of the upper and lower parts of the multiplier, K j multipliers (where K. p5: n, n is the fraction of operands, p is the number of I simultaneously processed bits of I operands) , the registers of the high and late parts of the result, the first and second adders of partial products | and the synchronization unit, the input of the first multiplier of each multiplied | body connected to the output of the corresponding | bits of the register of the multiplier, the outputs of the first and second adders partial works connected | ootvetstvenno with informatsidn- GOVERNMENTAL inputs and registers older | younger parts result which outputs are connected respectively to the first terms first Iinput and

.

23

eight

0

The second adders of partial products, the first, second and third outputs of the synchronization block are connected respectively to the shift inputs of the lower and higher parts of the multiplier and the multiplication resolution input K to multipliers, the fourth output of the synchronization block is connected to the shift input of the higher result register, the resolution input of the summation of the second partial adder products and the resolution enable entry of the lower part register of the result, the shift input of which is connected to the summing resolution input of the first sum ora partial products, write enable input of register high part result Q and fifth output synchronization unit, the start input and the clock input of which are respectively connected with the start input and the clock input of the device.

five

Absomotic burden Fig.d.

Claims (1)

Claim A device for multiplication, containing the register of the multiplicand, registers of the major and minor parts of the multiplier, K multipliers (where K is pZgp, η is the bit size of the operands, p is the number of operand bits processed simultaneously), registers of the highest and lowest parts of the result, the first and second adders of partial products and a synchronization unit, wherein the input of the first factor of each multiplier is connected to the output of the corresponding p bits of the register of the multiplicable, the outputs of the first and second adders of partial products are connected respectively to informational inputs of the registers of the highest and lowest parts of the result, the outputs of which are connected respectively to the inputs of the first terms of the first and second adders of partial products, the first, second and third outputs of the synchronization block are connected respectively to the shift inputs of the registers of the minor and senior parts of the multiplier and the multiplier resolution input K of the multipliers, the fourth output of the synchronization unit is connected to input 10 of the ^{shift house of the} Register of the highest part of the result, by the input of the permission to add the second adder of partial Zvezdov and the permission input to write the register of the younger part of the result of 15 theta, the shift input of which is connected to the input of the permission to sum the first adder of partial works, the input of the permission to write the register of the senior part of the result 2θ and the fifth output of the synchronization block,. the start input and the clock input of which are connected respectively to the start input and the clock input of the device. figb Figure 2. Fig.Z