SU1607008A1 - Device for recording digital information - Google Patents

Abstract

The invention relates to magnetic recording, in particular, to devices for recording digital information on a movable magnetic medium. The aim of the invention is to increase the recording level by narrowing the spectrum of the fundamental frequencies of the generated signal. In the device containing the input shift register 1, connected by a synchronization input through a divider 3 frequency to the synchronization bus 4 and directly to the counter input 5 cycles and outputs to the first inputs of the converter 7 codes, the output shift register 10 connected by the synchronization input through the first delay element 8 to sync bus 4, and the recording amplifier 13, additionally introduced a counting trigger 12, its input connected to the output of the register 10, and the output to the input of the amplifier 13, and the second el-connected in series 11 delay and corrector code 9 of the output shift register, information inputs connected to the outputs of the register bits, output to the second input of the register bits, the input of the second delay element connected to the output of the 5 clock counter, the output of the divider 3 is also bus output information request. 1 hp f-ly, 2 ill.

Description

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ABOUT

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The invention relates to the field of accumulation of information, in particular, to devices for recording digital information on a movable magnetic carrier.

The aim of the invention is to reduce the distortion due to the narrowing of the spectrum of the fundamental frequencies of the generated signal.

 Fig, 1 shows a functional diagram of the device; 2 is a functional; conversion scheme. codes.

160700 I

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A device for recording digital information, the functional scheme of which is shown in FIG. 1, contains a three-bit input shift register | connected to the information: the input to the information bus 2 by the synchronization input through the frequency divider 3 to the synchronization bus 4 and directly to the input of the counter 5 clock and bus 6 request information and outputs to the first (informational) inputs of the converter 7 codes; first 8 delay elements; corrector 9 of the code on the output shift register 10; second (clock) input of the converter 7 code in conjunction with the input of the second delay element 11, to which the code corrector 9 on the output shift register is sequentially connected, is connected to the output of a 5-stroke counter, the output shift register 10, containing 11 bits, is connected by the first bit ports. installation (2,3,4,5,7 and 8th bit) - to the corresponding outputs of the converter 7 codes, the second installation inputs (9th bit) to the output of the code 9 offset on the output shift register, the synchronizing input through the first, element 8 delay to the sync bus 4, output hundred After the serially connected counting trigger 12 and recording amplifier 13 to the output bus 14 of the device, and outputs of the bits (7, 8, 10, 11th bit) to the corresponding inputs of the corrector 9 codes on the output shift register 10.

Converter 7 of the output register codes will hold six elements AND 15-20, the combined first inputs of which are the second input of the inverter, the second inputs of the first to fourth elements And 15-18 are also about 7, are single and are the first information

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The converter input, the inputs of the second 16 and third 17 And elements are inverting, the third inputs of the second 16, third 17 and fourth 18 And elements, combined together, are the second information input of the converter, And the inputs of the second 16 and fourth 18 And elements are inverting, the third information input of the converter is connected to the second inputs of the first 19 and sixth 20 elements And, the outputs of all six elements 15-20 And connected to the corresponding outputs of the converter, in addition, the output of the fourth element And 18 is connected with the third input of the fifth element And 19, and this input is inverting.

In Fig. 1, the first 21, the second 22, and the third 23 inputs of the code converter, the first-sixth 24-29 code converter output, and the second code converter input 30 are indicated.

In this practical implementation example, the four-interval write signal is informed by the BNHM method with a ratio of the durations of the intervals:

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the digital input information is converted into eight-bit groups from which the recording signal is formed directly, each group being separated from the extra cycle following it, in which symbol 1 or symbol O is written. Symbol 1 is recorded only when . Previously, the transcoding information group ends with at least two zeros, and the next one also contains 5 at least two zeros at the beginning.

The information code converter in this example is produced as indicated in the code correspondence table.

The device, made in accordance with the scheme shown in figure 1, works as follows.

The sync pulses from sync bus 4 arrive at the inputs of the pulse frequency divider 3 and the first delay element 8. After dividing the frequency, the sodium pulses from the output of the divider 3 pulse frequencies are fed to the counter input 5 cycles

of the recorded information, the clock input of the input shift register 1 and the output bus 6 signal request information. The code of the recorded information, which enters the information bus 2, is recorded sequentially in the input shift register 1. The code signal from the outputs of the bits of the input shift register 1 is fed to the first (informational) inputs of the code converter 7, to the second (polling) input of which a signal is output counter 5 cycles.

1607008

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The new register is an OR-NOT element with five inputs, one of the inputs to which the signal from the output of the first delay element 8 is inverting. As a result, at the output of the code 9 offset on the input shift register, a signal will be generated only in cases when code zeros will be written in the seventh, eighth, tenth, and eleventh bits of the register.

Under the action of synchronization pulses coming from bus 4 synchronization.,. J l fci-fci viA ij. eh h MJiJUjji -t H Jrl L.-L.i and Pg1 -

as a result, at the output of the transducer, 5 zation through the first element 8 delay

L7 codes form a code group of signals corresponding to the code of the converted information.

The formation of the code signal in the code converter 7, the functional diagram of which is shown in FIG. 2, is provided by AND 15-20 logic elements performing the functions:

Y, X ,. .X2 z; 25

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, Y5 (X ,. Xg), where X ,, X2, signals at first

(informational) inputs of the code converter;

signals at the outputs of the converter codes; Z is the signal at the second input of the code converter. The signals from the output of the converter 7 codes, arriving at the inputs of the bitwise setting of the output shift register 10, are set on the second, fifth, seventh and eighth bits, register corresponding states. In this case, the first, sixth and ninth bits are in the zero state In the tenth and eleventh digits, the values of the last two digits of the previous group are stored.

Claims (2)

1. A device for recording digital 30 information containing an input shift register connected by an information input to a data bus, a synchronization input through a frequency divider to a synchronization bus and directly to the input of a clock counter and outputs to the first inputs of a code converter, the second input of which is connected to the output of a counter clock cycles, the output shift register connected by the first inputs of the bit set to the outputs of the code converter, the synchronization input through the first delay element to the sy hroniziruyuschey bus and a write amplifier whose output is vyho45 The house of the device, characterized in that, in order to reduce distortions due to the narrowing of the spectrum of the main frequencies of the write signal 50, a counting trigger is entered, the input is connected to the output of the output shift register, and the output is connected to the input of the recording amplifier, .i. bits of the output shift register, the output to the second input of the setting bits of the output shift 1607008 The new register is an OR-NOT element with five inputs, one of the inputs to which the signal from the output of the first delay element 8 is inverting. As a result, at the output of the code 9 offset on the input shift register, a signal will be generated only in cases when code zeros will be written in the seventh, eighth, tenth, and eleventh bits of the register. Under the action of synchronization pulses coming from bus 4 synchronization.,. J l fci-fci viA ij. eh h MJiJUjji -t H Jrl L.-L.i and Pg1 - the organization through the first element 8 delay the organization through the first element 8 delay (the delay time is determined by the completion time of the installation of the code on the output shift register 10) to the clock input of the output shift register 10, the transformed information code is sequentially inputted to the input of the counting trigger 12, forming the BBNM recording signal at its output. After amplification in the recording amplifier 13, the signal is fed to the output bus 14 of the device. The formula of the invention. neither 1. A device for recording digital information containing an input shift register connected by an information input to a data bus, a synchronization input through a frequency divider to a synchronization bus and directly to the input of a clock counter and outputs to the first inputs of a code converter, the second input of which is connected to the output of a clock counter , the output shift register connected by the first inputs of the bit set to the outputs of the code converter, the synchronization input through the first delay element to the sync and a recording amplifier whose output is output ohm device, characterized in that, in order to reduce distortions due to the narrowing of the spectrum of the main frequencies of the generated signal 0 of the record, a counting trigger is entered, the input is connected to the output of the output shift register, and the output is connected to the input of the recording amplifier. bits of the output shift register, the output to the second input of the setting bits of the output shift register, while the second input from the delay element is connected to the output of the clock counter, and the output of the divider Pulse frequency is also a bus for information request output signals. 2. The device according to claim 1, of which is that the code converter contains six AND elements, the combined first inputs of which are the second input of the converter, the combined second inputs of the first, second, third and fourth elements AND the first information input of the converter, while the inputs of the second and third elements And are inverting, the combined third inputs of the second, third and fourth elements of AND are the second information input of the converter, the inputs of the second and fourth elements inverting executed, the third data input connected to the body transformation second inputs of said fifth and sixth AND gates, the outputs of the six AND gates connected to their respective transducer outputs, a fourth output element and connected to the third input of the fifth AND gate, an inverting performed. 24 25 0 210 22 FIG 2 A 25 / N27 .28 29 023