SU1601768A1 - Adaptive receiver of relative bi-pulse signal - Google Patents

Abstract

The invention relates to telecommunications technology. The purpose of the invention is to increase the reliability with concentrated noise and to ensure that the input signal is lost. Adaptive receiver contains latch 1 transitions, 2 clock frequency selector, shaper 3 pulses, shaper 4 signals, shift register 5, signal decoder 6, first divider-decoder 7, first drive 8, trigger 9, first, second and third elements And 10, 11 and 12, the AND-HE element 13, the second divider-decoder 14, the fourth and fifth elements AND 15 and 16, the second drive 17, the sixth element AND 18. The received relative bi-pulse signal, which is a combination of three signals (information, clock and octet) are chained sequences coupled latch 1 transitions extractor 2, 3 shaper, shaper 4, the shift register 5 and the decoder 6 signal. Resetting synchronism is possible only with simultaneous fixation of loss of synchronism by the first drive 8 and the presence of synchronism by the second drive 17. 1 Il.

Description

The invention relates to telecommunications engineering and can be used in butt-receiving equipment of the main digital channel and in data transmission systems.

The purpose of the invention is to increase the reliability with concentrated noise and to ensure that the input signal is lost.

 The drawing shows a structural electrical circuit of the proposed adaptive receiver.

The adaptive receiver of the relative bi-pulse signal contains a latch 1 transition, a selector 2 clock frequency, a shaper 3 pulses, a shaper 4 signals, a shift register 5, a decoder 6 signals, the first divider - the decoder 7, the first drive 8, trigger 9, first 10, second 11 and the third 12 elements And, the element AND-NOT 13, the second divider-decoder 14, the fourth 15 and the fifth 16 elements And, the second drive 17, the sixth element And 18.

The receiver works as follows.

A relative bi-pulse signal is input to the latch 1 of the transitions, which is a combination of three signals; information, clock and octet (synchronization), the transmission of which eliminates the corresponding clock transitions. At the output of latch 1 of the transitions, narrow pulses are generated at the site of all transitions of the input signal. The clock selector 2 produces a harmonic oscillation, synchronous and in-phase with the instants of signal transitions, the amplitude values of this oscillation coincide in time with the instants of signal transitions, and the frequency of this oscillation is equal to twice the frequency of the received signal. The pulse shaper 3 generates from a harmonic oscillation a sequence of rectangular pulses with a duty cycle of two, the fronts of which coincide with the moments of transition through zero of the harmonic oscillation. The signal conditioner 4 serves to spread the short pulses received at the output of latch 1 of the transitions. The extended pulses from the output of the driver 4 of the signal are transmitted to the shift register 5, in which the serial code is converted into a parallel one, in each of the bits of which the information component and the clock pulses with the octet signal, i.e. a clock signal is a sequence of the form W ... 10W, .. 101 ...

For the main digital channel, the periodicity of the octet signal is 16 clock intervals, taking into account the information component. For this case, the shift register size 5 must be 16 bits.

A signal decoder 6, connected by 0 to the outputs of the shift register 5 cells with only even (or only odd) numbers, is designed to generate responses that appear every time a combination of 5 types 111 appears in its input signal ... 10, i.e. a combination that coincides with the clock sequence with an octet signal. The moments of occurrence of these responses coincide with the moments of the octet signal. 0 The first 7 and second 14 dividers-decoders have a division factor of the same as the period of the following octet signal, which is equal to 16.

In the mode of the established synchronization, the narrow pulses at the first output of the first divider-decoder 7 coincide in time with the moments of occurrence of periodically subsequent responses of the decoder 6 of the signal. At the same time, the fourth element 0 and 15 opens and its output pulse sets the first accumulator 8 to the initial state.

The information signal is generated by the trigger 9. Information input 5 of which is connected to the output of the corresponding bit of the shift register 5, and the clock input is connected to the second output of the first divider decoder 7, which is divided into two clock signal from the output of the imager 3 pulses.

At the output of the first element And 10 acts octet (synchronizing) signal.

45 When a single error in the incoming clock signal at the output of the fourth element And 15 does not appear pulse, the first drive 8 is not installed and is recorded through the information input connected to the 50 inverse output of the decoder 6 signal error signal. If the sync signal appears again in the next cycle, then the error signal recorded in the first accumulator 8 is erased. Thus, single errors in the receiving sync signal do not result in a loss of the synchronizing pulse at the corresponding output of the adaptive receiver.

In the state of established synchronism and in the absence of errors, the sync signal at the output of the second divider-decoder 14 has a narrow pulse that coincides with the moments of receipt of periodic responses at the direct output of the decoder 6 signal.

In this case, the second accumulator 17 fixes the state of the established synchronization confirmed in each cycle, the NAND element 13 is blocked by a signal from the inverse output of the signal decoder 6 and the clock sequence from the output of the imaging unit 3 pulses continuously passes through the second element 11 on the clock input of the second divider - decoder 14, and the third element And 13 is blocked by the inverse input and the settings to the initial state of the second accumulator 17 do not occur.

When a single error appears in the received sync signal in this cycle, the AND-HE element 13 is not blocked, which leads to locking the second element 11 and unlocking the third element 12, i.e. The clock pulses are interrupted by the second divider-decoder 14 and the second accumulator 17 is set to the initial state. The clock frequency interruption continues until the next response appears on the forward output of the decoder 6 of the signal, from which the second divider-decoder 14 starts counting At the end of this cycle, depending on whether or not the response appears at the given moment, the second accumulator .17 will either fix it or re-establish itself in the initial state.

With actual loss of synchronism, the moments of occurrence of pulses at the first output of the first divider-decoder 7 do not coincide with the moments of receipt of the responses of the decoder 6 signal and the first drive 8 will detect loss of synchronism after a certain number of cycles.

At the same time, the combination of the element IS-NE 13 of the second element 11 of the second divider decoder 14 performs, in accordance with the described principle, the search for a new temporal position of the periodic responses of the decoder 6 signal. After the synchronism is fixed by the second accumulator 17, the fifth element AND 16 is triggered and the first divider-decoder 7 is re-phased through its installation input and thus synchronism is restored.

It is advisable to choose the accumulation factor of the first accumulator 8 more than the accumulation coefficient of the second accumulator 17.

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Thus, reconfiguration in the proposed adaptive receiver is possible only with simultaneous fixation of the loss of synchronism by the first drive 5 and the synchronism by the second drive 17.

This results in achieving the goal with packetized errors and high error rates in the communication channel.

0 When the connection is interrupted (error errors), when the first drive 8 detects a loss of synchronism, and the second drive 17 does not detect it, the sixth element AND 18 is activated and an alarm occurs at the corresponding output of the adaptive receiver. At the same time, the output of an octet (synchronizing) signal is blocked, and as an information signal, due to the impact of an alarm signal on the setup input of the trigger 9 and the output, a signal from continuous single parcels is issued corresponding to the alarm indication signal, which is consistent with the principles

5 maintenance channels and paths.

Claims (1)

Invention Formula 30Adaptive Relative Receiver bi-pulse signal containing serially connected latch transitions, a clock frequency extractor, a driver. pulses, a driver 35 of the signal, to the second input of which the output of the latch transitions are connected, and a shift register, the second input and outputs of which are connected respectively to the output of the pulse driver and to the inputs of the decoder 0 signal, the inverse output of which is connected to the information input of the first accumulator, and with the information input of the trigger, the output of which is the information output of the receiver ka, entrance and 5, the clock and clock outputs of which are, respectively, the input of the transition lock, the output of the first element I, to the first input of which the clock input of the first accumulator is connected, and 0 is the trigger input of the trigger, which is connected to one output of the first divider decoder, the other output of which is connected to the clock input of the first accumulator, as well as the second and third element AND and the element. 5 I-NOT, the output of which is connected to the first input of the second element I, to the second input of which the output of the pulse shaper is connected, characterized in that, in order to increase the reliability with concentrated interference and provide control of the input signal loss, the fourth, fifth and fifth And elements, the second divider-decoder and the second drive, whose information input is connected to the direct output of the signal decoder, the inverse output of which is connected to the first input of the NAND element, and to the second input of the fourth element a And, the first and third inputs and output of which are connected respectively to the output of the pulse driver, which is connected to the clock input of the first divider decoder, with the first input of the first element And, to the second input of which the output of the sixth element And is connected, and with the installation input of the first accumulator the output of which is connected to the first input of the sixth element AND, the output of which is the signal output of the receiver and is connected to the installation input of the trigger, and the first input of the fifth element I, the second and third inputs and the output of which are connected respectively to the output of the second accumulator, which is connected to the second input of the sixth element And, with the output of the second divider decoder, which is connected to the clock input of the second accumulator , and with the installation input of the first divider decoder, while the output of the second divider decoder is connected to the second input of the NAND element, the output of which is connected to the first input of the third And element, the second input and output of which respectively, are connected with the second input of the second element I, the output of which is connected to the clock input of the second divider-decoder, m with the installation input of the second storage device.