SU1598208A1 - Slave tv synchrogenerator - Google Patents

Abstract

The invention relates to television. The purpose of the invention is to improve the phasing accuracy, to enable work on different decomposition standards and to obtain different output signals. In the absence of an external synchronization signal, the operation takes place offline. Clock pulses (TI) are received from the clock pulse generator (GTI) 3 to the input of the first counter 4 and to the clock inputs of D-flip-flops 5, from counter 4 to the address inputs of the programmable fixed memory (VPT) 6. After the countdown of a certain number of TI At the output of the BPS 6, programmed synchronization signals occur, the frequency of which is higher or equal to the frequency of the lines. At the output of the BPS 8, connected to the input of the element 2ILI 12, a signal arises which, having passed through the counter 7, has a frequency of the fields. The purpose of the invention is achieved by the introduction of the multiplier 1 frequency, the selector 2 of the fronts of the clock pulses, two elements 2 OR 11 and 12, the elements 3I-HE 9 and 10. 1 Cp f-ly, 2 ill.

Description

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This invention relates to | communications equipment and used in television systems with centralized synchronization of the sensors of a television (TV) signal.

The aim of the invention is to improve the accuracy of phasing, to enable work on different decomposition standards and to obtain various forms of output signals.

FIG. 1 shows a block diagram of a slave clock generator; FIG. 2 is a timing diagram of signals at various points of the slave television synchronizing generator.

The slave television clock generator contains a multiplier of 1 frequency, a selector of 2 clock fronts, a crystal oscillator of 3 clock pulses (GTI), the first counter. D-flip-flops 5, the first block 6 of the read-only permanent memory (BPPP second counter 7, the second STB 8, the first 9 and the second 10 elements ZI-PE, the first 11 and the second 12 elements 2 OR. Trigger 13 and shaper 1h output signals .

The slave TV sync generator works as follows

In the absence of an external synchronization signal receivers (SSP) work takes place offline, mode. Clock pulses from the generator 3 clock pulses are fed to the input of the first counter 4 and to the clock inputs of D-triggers 5. The bit outputs of the first counter 4 are connected to the corresponding inputs of the BFPT, the output of the first counter k is connected to the counting, trigger 13 input The output of which is also connected to the address input of the BPSP. Connection of the bits of the first counter k and the trigger 13 with the address inputs.

STI 6 is produced as the discharge bits of the first counter 4 and trigger 13 and the address inputs of the STI 6, respectively, increase.

After counting a certain number of clock pulses K (K 1,

where Tc is the period of the frequency of lines,

T, I / CS I with 11 vx (g g. ", -,

clock period) at the output of the BPS 6 connected to the second input of the first element 2IL 11, a programmed signal will appear (Fig, 2h) which through the first element 2 OR i will go to the installation input of the first counter i and set it to O,.

Thus, a clock frequency is provided to a double line frequency. One of the STP 6 outputs is programmed with a double horizontal frequency signal, which is fed to the input of the second counter 7. At the BPS 6 outputs connected to the information inputs of the D-flip-flops St, the output synchronization signals are programmed whose frequency is higher than or equal to the line frequency. From the output of the first counter 4, a double line frequency is fed to the counting input of the trigger 13, which divides it up to the line frequency. The bit outputs of the second counter 7 are connected to the address inputs of the BPS 8 as the bits of the counters and the address inputs of the BTP 8 increase, respectively.

After reading the second counter 7 of a given number of pulses at the input (625 for the USSR broadcast standard) at the output of the BPS 8 connected to the input of the second element 2 OR 12, a signal will appear (Fig. 2g), which through the second element 2ILI 12 will go to the installation input of the second counter 7 and install it in O.

Thus, the division of the double line frequency to the frequency of the fields is ensured. The outputs of the BPS 8 connected to the information inputs of the D-flip-flops 5, field frequency synchronization signals are programmed. The outputs of the BPS 8 connected to the address inputs of the higher bits of the PPP 6 are programmed frequency signals of 2.5 and 7.5 N fields (N - line length), which provide the MTP at one of the STP 6 outputs by programming it. On the output of the BPS 8, which is connected to the third inputs of the 3 I-NE elements, a signal of the field frequency of 7.5 N is programmed (Fig. 2d). The output sync signals from the STP 6 and 8 outputs to the information inputs of the D-trip character 5 are clocked and from the outputs of the D-flip-flops 5 are fed to the output of the slave television clock.

When a slave television sync generator arrives at the input of an external ERP, frequency multiplier 1 generates an output signal of the external SRQ monica on the output. Frequency multiplier 1 may contain two or three

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steps of multiplication. The number of stages of multiplication depends on the nominal frequency of the generator 3 clock pulses. With a clock frequency of 1 - 1.5 MHz. two steps are sufficient, with a higher clock frequency (e.g. 10-12 MHz) three steps of multiplication are required.

Clock pulses from the last stage of the multiplier 1 are fed to the generator input of 3 clock pulses and force it to work on the p-harmonic of the external SCF, with the result that the output clock signal frequency will correspond to the frequency of the rows and fields of the external SCF, from the external SCF input (Fig. 2a) enters the input of the selector 3 fronts of clock pulses. The selector 2 of the fronts of the clock pulses is made on the logical elements 2I-NOT on which the SCF is delayed, and then narrow pulses are formed from the edges of the SCF (Fig. 25) and from the slits of the SCF (Fig, 2L). From the first output of the selector 2, narrow pulses from the edges of the ERPs are used to phase the generated signals along the line. They arrive at the first input of the first element 3 AND-NOT 9. The second input of the first element ZI-NOT 9 receives pulses of the frequency of the negative polarity lines from one of the exits of runway 8 (Fig. 2c). Pulse duration t, must be 2T. The third input of the first ZI-NE unit, PA, from one of the outputs of the BPS 8, receives pulses of the frequency of negative polarity fields of 7.5 N duration (Fig. 2d).

In the case when the line frequency signals generated by the slave television synchro generator are not phased relative to the external ERP. Narrow pulses from the edges of the external ERP pass through the ZI-NE 9 and 2 OR 11 elements to the input of the installation of the first counter 4 and set it to the initial state - O. The time position of the signals programmed in the BTP is set relative to the initial state of the first counter four.

The pulses generated from the SPS CUTS, from the second output, the selector 2 (Fig. 2e) are fed to the input of the second element ZI-NE 10. The other input of the second element ZI-NO 10 receives pulses of double horizontal frequency of positive polarity from one

98208

from the outputs of the BPS 6 (Fig. 2e). The temporal position of these pulses is set so that they coincide with the pulses generated from the slices of the equalizing pulses of the external ERPs (Fig. 2e). With a symmetric arrangement of the pulses (Fig. 2e) relative to the slices of the equalizing pulses

, Q their duration should not exceed 1 WKC. The third input of the second ZI-NE 10 element from one of the BNP output terminals V. receives pulses of frequency of negative-polarity fields with a length of J5, 7.5 N (Fig. 2d). In case of a mismatch with the leveling pulses of the external ERP, the pulses generated from the sections of the leveling pulses will pass through

20 second element ZI-NOT THAT. The first impulse that passed through the second element ZI-NOT 10 will go through the second element 2 OR 12 to the installation input of the second counter 7 and set it to O,

25 as a result of which phasing of the signals of the field frequency will occur, and at the third inputs of the elements ZI-HE 9 and 10 there is a signal (Fig. 2d) that prevents further passage

30 phasing pulses through the second element ZI-NOT 10. This signal will also go to the input of the first element ZI-NOT 9 and will prohibit the passage of phasing pulses through it with a double line frequency. If it turns out that the frequency pulses of the rows in the sequence of phasing pulses (Fig. 26) do not coincide with the pulses from the output of the ATT 6 (Fig. 2c), then the phase pulse passes through the first element ZI-HE 9 to the setup input of the trigger 13; will set it to 0, and all signals from exits of runway 6 will be phased relative to the VTS interposition. Further passage

phasing pulses at the installation inputs in About counters and 7 and three 13 will be prohibited. After phasing, the operation of the counters 4 and 7 will be controlled by pulses from STD 6 and 8 via elements 2 OR 11 and 12, respectively.

When the slave TV clock synchronizer of the external SSP disappears at the input, the clock pulse generator continues to operate at its own frequency and the clock signals at the outputs are retained.

7. 1598208

The slave television clock generator has a high stability in operation and a short time to synchronization, since the possibility of synchronization failure due to the transient process caused by the PLL circuits and the phasing circuit is eliminated, it is phased with high accuracy and has a wide capture band.

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Claims (2)

1. The slave television synchronizing generator, which contains successively connected: a Warme clock generator (GTI), the first counter and a trigger, as well as the second counter and driver of the output signals, while the discharge outputs of the first counter are connected to the first group address input of the rapper output signals, the trigger output is connected to the second address input of the output signal generator, the bit outputs of the second counter are connected to the third group address input of the output signal generator, and the cycle The new input of the output driver is connected to the output of a quartz GTI, characterized in that, in order to increase the phasing accuracy, to enable work on different decomposition standards and to obtain various output signals, a frequency multiplier, a clock edge selector, two elements 2ILI, two element ZI-NOT, while the input of the frequency multiplier is connected to the input of the front-edge selector of the clock pulses and is the input of the slave TV sine generator, the output of the frequency multiplier is connected to using the quartz GTI, the first output of the sync pulse front selector through the serial but connected first ZI-NE element and the first 2IL element is connected to the setup input of the first counter, the second output of the sync pulse front selector through 0 20 25 thirty 35 40 45 50 but connected to the second element ZI-NOT i and the second element 2IL is connected to the installation input of the second counter, the counting input of which is connected to the first output of the output signal generator, the second input of the first ZI element is NOT connected to the second output of the output signal generator, and the output of the first ZI element -NOT connected to the setup input of the trigger, the second input of the first element 2IL is connected to the third output of the output driver, the second input of the second element ZI is NOT connected to the fourth output of the output driver x signals, the second input of the second element 2IL is connected to the fifth output of the output driver, the third inputs of the first and second ZI-NE elements are connected to the sixth output of the output driver, the seventh group output of the output signal generator is the output of the slave television clock generator, 2. A synchronous generator according to claim 1, characterized in that, in an output driver comprising two blocks of programmable fixed memory and D-flip-flops, whose inputs are connected respectively to information outputs of blocks of programmable fixed memory, the first and second outputs of the second The npoi of the frame memory is connected to the first and second inputs of the first block of programmable fixed memory, respectively, the first, second, third and fourth outputs of the first block of programmable constant memory are responsibly, the same output of the output driver, the third and fourth outputs of the second programmable memory block are the fifth and sixth outputs of the output driver, and the D-flip-flop outputs are the seventh group output of the output signals.  “,