SU1591189A1 - Signal decoder - Google Patents

Description

The invention relates to computing and communication technology. Its use in systems for transmitting and storing digital information improves the accuracy of decoding. The device contains an element NOT 2., elements AND 3-6, dividers 9.10 frequencies and elements OR 11,12. Due to the introduction of a clock generator 1, the elements And 7.8, the counting trigger 13 and the CB-triggers 14-16, all odd'o distortions are detected in the device; the multiplicity and part of the distortion is even ’; multiplicities. 3 il.

1

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The invention relates to computing and communication technology and can be used in systems for the transmission and storage of digital information.

The purpose of the invention is to improve the decoding accuracy.

FIG. 1 shows a functional diagram of the device; in fig. 2 and 3 are timing diagrams explaining the operation of | θ devices.

The device contains a generator 1.

clock pulses, the element is NOT 2, the first is the sixth elements AND 3-8, the first 9 and second 10 dividers. frequencies, the first 11 and second 12 elements OR, the counting trigger 13 and the first - the third KB trigger 14 -16. In FIG. 1 indicated informational and control outputs 17

and 18. 20

Divider 9 (10) frequency can be performed on the counter 19 (20) and the decoder 21 (22).

The device is intended for decoding a bi-pulse signal (man-chester code), in which a binary unit is represented by a two-level signal with a transition in the middle of a clock interval from a high level to a low one, and a binary zero - a reverse βθ transition. The duration of the half-cycle (when the level is unchanged) is 2.

The device works as follows. ββ

The signal to be decoded, which is a bipolar bi-pulse signal (Fig. 2a), goes directly to one of the inputs by elements 3, and through the element NOT dd 2 to one of the inputs of the And 4 element.

The other inputs of the elements And 3 and 4 receive pulses from the generator 1 with the frequency ой Ζ> · £ _Η (Fig. 26), where £ c = 1 / 2C

Ζ is the frequency division factor of dividers 45 and 9 and 10, chosen from the condition for obtaining the necessary accuracy of signal registration.

Element And 3 opens for a time equal to the length of the received impulse - βθ

sa positive polarity. During this time, Ζ pulses from generator 1 (Fig. 2c) pass through it. The next negative momentum of a binary unit is inverted on the element NOT 2 $$

and opens the item. And 4, through which also passes Ζ pulses from the generator 1. Thus, at the outputs of the elements And 3 and 4 appear packs on

Ζ pulses corresponding to positive and negative pulses of the binary sequence (Fig. 2c, d). If two pulses of positive or negative polarity are received in succession, 2Ζ pulses from generator 1 appear at the output of elements 3 or 4 (Fig. 2d).

When a positive pulse of a binary unit is received, it opens and starts counting the counter 19 of the divider 9, which, after / 2 from the beginning of the pulse, counts to Ζ / 2. Enabled at the output of the counter 19, the decoder 21 is set to Ζ / 2 and at its output is a short pulse (strobe), which corresponds to the middle of the received positive pulse.

(Fig. 2d). The counter 19 counts to Ζ, at this time the reception of the first positive impulse ends, the element And 3 closes and the count stops. Next comes a negative pulse, so it starts counting the counter 20 of the divider 10, which counts to Ζ / 2 and the decoder 22 at its output issues a strobe (Fig. 2e), which resets the first divider 9 to zero, and through the OR 11 element goes the counting trigger 13. The second divider 10 also reaches to Ζ, after which the first divider 9 begins to count, which by the second gate (after Ζ / 2 generator 1 pulses) resets the second divider 10.

If two consecutive positive or negative polarity signals are received in succession, an element E 3 or 4 is opened in continuation of 2 ^ and counts one of the dividers 9 or 10, which reaches Ζ / 2, after which its decoder 21 or 22 generates a strobe in the middle of the first pulse and the counter 19 or 20 continues to count to Ζ, goes to the zero state and counts from the first to Ζ / 2 pulse, at the moment of occurrence of which a second strobe is output in the middle of the second information pulse by the decoder 21 or 22 (Fig. 2e). Next, the counter counts to Ζ and the counting stops, since the corresponding element AND 3 or 4 closes at the input of divider 9 or 10. The contents of counter 19 or 20 of this divider 9 or 10 are reset by the strobe pulse of another divider when receiving the next information pulse. Gates with exits de5

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units 9 and 10 are combined on the element OR 11. As a result, at the output of the element OR 11, gating pulses are obtained, shifted relative to the edges of the received pulses by £ / 2, ie in the middle (Fig. 2g).

The timing diagrams in FIG. For, b, c, d repeat the diagrams in figa, d, 'e, g. With the help of them, the processes of de-conversion of bipolar signals into binary signals and distortion detection are shown. To form a clock interval, short pulses (Fig. 3g) are fed to a counting trigger 13, at the output of which pulses are received with a frequency of £ _{7 and} =

= 1/2 ^ (fig. Rear). These pulses are fed to the inputs of the elements And 5 and 6, the second inputs of which are supplied with pulses from the outputs of the dividers 9 and 10 (fig.Zb, 20). As a result of this signal from the output of the element And 3 set the trigger 14 to one, and the signals from the output of the element And 6 reset it to zero. At the output of this trigger 14, 25 binary information is generated (Fig. Ze).

FIG. Zj shows a distorted bipolar sequence of signals. Distorted signals are shaded.

In this case, the analysis of the structure of the bi-polar signal for the detection of distortions is as follows. At each clock interval, it should appear with an undistorted bipolar signal with one strobing pulse from the outputs of dividers 9 or 10.

From FIG. Зж, з, and it is clear that the first and second distortions cause the appearance of the second gating pulse from the output of divider 9 at the clock interval up to (Fig. Zh, h), and the third distortion - the second .terbating pulse from the output of divider 10 ka to the clock interval .

(Fig. Zzh, and). This is used to detect distortion with the help of triggers of 15 and 16, elements AND 7 and 8, and element OR 12. If there are no distortions on the clock interval, the trigger 15 or 16 is set to one and reset to zero. At the first or ·; 50 second distortion trigger 15 on the front from the output of the element And 5 is set to one, resulting in the opening of the element And 7 and the next pulse from the output of the divider 9 passes through 55 through the elements And 7 and OR 12 to the output 18 and is given as a signal "Erase "In the external decoder. The trigger 16 and the elements AND 8 and OR 12 work similarly

with the appearance of the third distortion (Fig. ZJ).

The proposed device for decoding ensures that all distortions of odd multiplicity and part of distortion of even multiplicity are ordered, except when inverting two pulses in a row at the clock interval, for example, a bipolar signal of the “+” type transforms into a signal and therefore, is capable of Distortion detection This decoding method is not worse than even parity code. Therefore, the probability of not detecting distortion in the device

HGN I

1 / + ¹ Р (1-Р)

where is 5

m is the word width of the input code;

P - the probability of symbol distortion.

The proposed device can be used as an internal decoder, if the Manchester code is used instead of the internal code with a parity when using concatenated coding. In this case, since there are no redundant CHARACTERS; transfer rate will increase.

You can use the NDVP code (for example, NDVZ) as a code in place of the Manchester code.

Claims (1)

Claim A device for decoding signals containing the first element Ιί, the first input of which is NOT connected to the first input of the second element I, the outputs of the first, ι: And the H elements of the element are connected to the clock inputs of the same frequency dividers, the outputs of which are connected to the first inputs of the third and fourth, respectively elements And and respectively to the first and second inputs of the first element OR, the second element OR, characterized in that, in order to increase the reliability of decoding, the counting trigger has been entered into the device, the third and third sixth elements AND and the clock generator, the output of which is connected to the second inputs of the first and second elements AND, the input of the element is NOT the input of the device 1591189 eight WA, the first input of the fifth element AND is combined with the K-input of the third KTrigger and the input zeroing of the second frequency divider and connected to the output of the first frequency divider, the input zeroing of which is combined with the first input of the sixth element AND and -K-input of the second short-trigger and is connected to the output of the second frequency divider, the output of the first element OR is connected to the input of the counting trigger, the output of which is connected to the second inputs of the third and fourth elements AND, the output of the third element AND is connected to the 8 inputs of the first and second short-circuits, output of the solid element I is connected to the 3rd input of the third KZ-flip-flop and to the input of the first KZ-flip-flop, the output of which is the information output of the device, the outputs of the second and third KZ-triggers are connected to the second inputs of the fifth and sixth And, respectively, the outputs of which are connected to the corresponding inputs of the second OR element, the output of which is the control output of the device. W ..., I _I_I I I I 2 1591189 ^Mr. III ι ι ι I ι ι ι ι_I III tz