SU1582343A1 - Device for synchronizing pulses - Google Patents

Abstract

The invention relates to the field of automation and computing. The aim of the invention is to improve the reliability of the device when using D-flip-flops, asymmetrical in the installation inputs. The device contains two synchronous D-flip-flops, the C input of the first of which is connected to the control signal bus, the R input with the setup signal bus, D-input with the logic zero signal bus, C- and S-inputs of the second D-trigger connected to each other and connected to the bus clock pulses, the unit output of the second D-flip-flop is connected to the S-input of the first D-flip-flop, connected by its single output to the D-input of the second D-flip-flop. 2 Il.

Description

This invention relates to automation and computing.

The purpose of the invention is to increase the reliability of the device when using b-flip-flops, asymmetric on the installation inputs.

FIG. 1 shows a block diagram of the device; in fig. 2 - time diagrams of his work.

The device for synchronization of pulses contains two synchronous D-flip-flops 1 and 2 "C-input D-flip-flop 1 is connected to the bus 3 of the control signal, R-input - with the bus 4 of the installation signal, and D-input - with the bus 5 signal of the logical zero .

The C and S inputs of D-flip-flop 2 are interconnected and connected to the bus 6 clock pulses, the single output of D-flip-flop 2 is connected to the S-input of D-flip-flop 1 connected

its single output to the D-input of the D-flip-flop 2.

FIG. 2 are designated: a - a sequence of clock pulses; b - synchronized pulses of short duration; c — single output of D-flip-flop 1, d — output of synchronized pulses of negative polarity; d - output of synchronized pulses of a positive gender.

The device works as follows.

After the supply of the power supply device, it is automatically set to the ready state for synchronization, since in the case of a spontaneous D-flip-flop 1 being set into the O state, the first clock pulse received at the C-input of the D flip-flop 2 transfers it to the zero state and the signal from the single output D-trigger

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with

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pa 2 transfers the D-grigger I to the single state. After the clock pulse terminates on the bus 6 clock pulses, the potential zero, arriving at the S input of the D flip-flop 2, translates it into a single state. Thus, in the absence of secondary pulses, both D-flip-flops 1 and 2 are set to one.

When a synchronized pulse arrives through the bus 3 of the control signal to the C input of the D-flip-flop 1, it goes to the zero state on the leading edge of the positive synchronized pulse, the zero signal from the single output of the D-flip-flop 1 goes to the D input of the D-flip-flop 2 and on the leading edge of the synchronizing pulse, the 0-flip-flop2 perekhorit to the zero state.

The zero state of the D-flip-flop 2 is maintained for the period following the clock pulse, since after its termination the zero signal at the S-input of the Trigger 2 translates it into a single state. The zero state of D-flip-flop 2 is a synchronized interval, the duration of which is equal to the duration of the synchronizing pulse. In this case, a synchronized output pulse of positive polarity is generated at the zero output of D-flip-flop 2, and a negative polarity at the single output.

The pulse from the single output of the D-flip-flop 2 is fed to the S-input of the D-flip-flop 1 and translates it into a single state regardless of the presence of a signal at the C-input. Thus, at the end of the clock pulse, the circuit is in the ready state, since both D-flip-flops 1 and 2 are in a single state.

When using the device to synchronize two sequences of non-coincident pulses, the C-input of D-flip-flop 1 serves the first sequence, and the R-input of D-flip-flop 1 - the second sequence.

In this case, the pulses at the R input must have a duration shorter than the duration of the clock pulses, since the D-flip-flop 1 is transferred to the zero state by the signal at the R-input not only along the leading edge of the pulses, but also during the entire interval equal to the duration of the input impulse that with large durations of impulses at the R-input of D-flip-flop 1 can lead to repeated false triggering of the device. Otherwise, the operation of the device in the mode of simultaneous synchronization of two sequences has no special features.

Claims (1)

Invention Formula A device for synchronizing pulses containing two synchronous D-flip-flops, the C input of the first of which is connected to the control signal bus, the R input — with the installation signal bus, D-input — with a logic zero signal bus, and the C input of the second trigger Connected to a clock pulse bus, characterized in that, in order to increase the reliability of the device when using D-flip-flops, asymmetrical at the installation inputs, the direct output of the second flip-flop is connected to the S-input of the first flip-flop, connected by its direct output to the D-input sec wigger, whose S- and C-inputs are interconnected. Jut PP P Ltl Phie.1