SU1550602A1 - Pulse generator - Google Patents

Abstract

The invention relates to a pulse technique. The goal — improving the speed — is achieved by introducing the pulse element OR 3 and new functional connections into the generator, which eliminates the effect of the delay of the subtracting counter 2 on the minimum period of the signal generated at the output of the pulse generator, and thereby increase the speed of the latter. The pulse generator contains a reference frequency generator 1, subtracting counter 2, control trigger 4, variable delay element 5. 1 il.

Description

The invention relates to a pulse technique and can be used in the development of radio measuring devices. 5

The aim of the invention is to increase the speed of the pulse generator.

The drawing shows a structural diagram of the proposed generator jq pulses.

The pulse generator comprises a reference frequency generator 1, subtracting the counter 2, the OR element 3, the control trigger 4 and the variable delay element 5.

The output of the pulse generator 1 is connected to the synchronizing input of the trigger 4 of the control and to the counting input of the subtracting counter 2, all 20 bit outputs of which, except the youngest, are connected to the inputs of the element OR 3, the output of which is connected to the recording permission input of the subtracting counter 2 and to the information input of the trigger 4 25 control, the first output of which is connected to the input of the variable delay element 5, the output of which is connected to the output bus and to the installation input of the trigger 4 control, the second jq output of which is connected to the input of the unit ki generator 1 reference frequency.

The device operates as follows. 25

Suppose that at the first output of trigger 4 and, accordingly, at the blocking input of generator 1, there is a potential that allows generation. The pulses from the output of the generator 1 are fed to the count-up | 1st input of the counter 2 and the synchronizing input of the trigger 4 control. Suppose that counter 2 is set to N. At the information input of trigger 4, there is a potential at which 45 this switch does not switch over to the clock input.

Next, the state of counter 2 changes in the direction of decreasing the number Ν. When passing a certain number of input pulses at the output of the OR 3 element and, accordingly, at the information input of trigger 4. a potential arises that fixes the zero state of the counter outputs connected to the OR 3 element. The corresponding potential is fed to the write enable input of counter 2, preparing it for recording the number N from the setup inputs of this counter (not shown in the drawing). Therefore, with the arrival of the next pulse of the generator 1, the trigger 4 of the control switches and the number N is written to the counter 2. At the output of the OR 3 element, the potential changes to the opposite. From the first output of trigger 4, the potential that prohibits generation is supplied to the blocking input of generator 1. Generation of oscillations of the reference frequency ceases. At the same time, the voltage potential obtained by switching the trigger 4 on its second output, passing through the variable delay element 5, is delayed by the set value, goes to the installation input of the trigger 4 and switches it to the initial state. At the first output of the trigger 4 and to a blocking input of the generator 1 there is a potential that allows generation. The output of the generator 1 appears pulses of the reference frequency. The process is then repeated. In the case when N = 1 is set at the installation inputs of the counter, at the output of the OR 3 element there is always a potential that allows the trigger 4 of the control to fire, i.e. with the arrival of the next pulse of generator 1, the trigger 4 of the control switches to a state in which a potential inhibiting generation appears on the blocking input of the generator 1 until a potential returns the trigger 4 to the installation input via the feedback circuit from the output of trigger 4 of the control control in the initial state.

Thus, the value of the minimum value of the period of the pulse generator is not affected by the delay of the signal along the circuits of the counter 2. In this case, the change in the period of the output signal of the device within one clock interval of the generator 1 is carried out by changing the delay of the variable delay element 5.

The exclusion of the effect of the delay of the counter 2 on the value of the minimum value of the period of the output signal of the device allows to increase the speed of the proposed pulse generator in comparison with the known one due to the direct exclusion of this delay from the value of the generated period, and due to the reduction of the clock interval of the generator 1.

Claims (1)

Claim A pulse generator comprising a reference frequency generator, a variable delay element, a subtracting counter and a control trigger, the first output of which is connected to the input of a variable delay element, the output of which is connected to the output bus and to the 15th installation input of the control trigger, the second output of which is connected to the generator input the reference frequency, the output of which is connected to the counting input of the subtracting counter, characterized in that, in order to improve performance, an OR element is inserted into it, the inputs of which are connected to all times yadnym subtracter counter outputs except Jr. output of OR element connected to the write enable input of the counter and the subtractor to control data input flip-flop, a clock input terminal coupled to the output of the reference oscillator.