SU1547081A1 - Device for correction of errors - Google Patents

Abstract

The invention relates to telecommunications and can be used in digital information transmission systems. The device extracts the pulses of the received code combination with the smallest amplitude (least reliable) for their subsequent decoding, which increases the reliability of the device. The device contains a linear unit 1, analog-to-digital converter 2, distributors 3.12 pulses, memory blocks 4.5, memory registers 6.1-6.N and 7.1-7.N, delay blocks 8.16, comparison block 9, trigger 10, element 11 and block 13 elements And 14. 2 ill.

Description

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The invention relates to telecommunications and can be used in digital information transmission systems.

The aim of the invention is to increase the reliability of the device.

Figure 1 shows the functional diagram of the device; Fig. 2 is a functional block diagram comparison.

The device contains (Fig. 1) linear block t, analog-to-digital converter 2, first pulse distributor 3, p.rvy and second blocks b and 5 of memory, made on registers 6 and 7 of memory, first block 8 of delay, block 9 comparison, the trigger 10, the element 11, the second distributor 12 pulses, the block (matrix) 13 elements And 1, the drivers 15 pulses and the second block 16 of the delay.

The comparator block contains (Fig. 2) the elements 17 - Comparative ST (selection of a larger number), the elements NOT 32 - 46 decoders 7 - 52.

The device works as follows.

The information input of the device receives an analog voltage from the output of the binary signal receiver, and the control input of the device is supplied with control pulses from the output of the clock pulse generator of the first decision circuit of the binary signal receiver.

The analog voltage is fed to the input of block 1, in which the bipolar voltage is converted to unipolar, after which the output of block 1 goes to the information input of the converter 2, to the control input of which is connected the output of the clock generator of the receiver of binary signals. The leading edge of the clock pulse forming the next symbol of the code combination, acting on the control input of the converter 2, converts the analog voltage to digital form. The code combination of the corresponding analog signal level is fed to the information inputs of registers 6, the number of which is equal to the number of characters of the message code combination. The control inputs of registers 6 receive pulses from the outputs of the first distributor of 3 pulses, to the input of which

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clock pulses are given. The clock pulse forming the first character of the message code combination is fed to the first output of the distributor of 3 pulses. The leading edge of the pulse at the first output of the distributor 3 allows you to record information from the output of the converter 2 into the register 6.1. The clock pulse forming the second symbol of the combination acts on converter 2 with a leading edge, which allows fixing the signal level corresponding to the moment of the leading edge of the clock pulse at its output, and the falling edge of the second clock pulse received at the second output of the distributor 3 records this information in the register 6.2. The clock pulse forming the last character of the combination will write the information about the level of the last character to the register 6.p. The clock pulse of the last character is a control pulse for writing information into registers 7.1-7.p. This pulse from the last output of the distributor 3 is delayed in block 8 for a time greater than the duration of the clock pulse, but less than the period of the clock pulse, which allows rewriting information from registers 6 to registers 7 until the clock pulse that forms the first character of the subsequent message code combination .

The values of the voltage levels of the symbols of the combination, recorded in registers 7, are fed to the inputs of the comparison block 9, in which the values of the levels are compared in pairs with each other. At outputs 9.1.1 to 9.1.t, information is generated about the relative value of the level stored in register 7.1, at outputs 9.2.1 to 9.2.t - information about the value of the level stored in register 7.2, etc. The appearance of a logical unit at one of the outputs 6.1.1, 6.2.1, ..., 6.n.1 indicates the smallest value of the character level stored in the corresponding register. The signal of the logical unit at one of the outputs 9.1.2, 9.2.2, ..., 9.p.2 indicates the second small value of the symbol level, and the signal of the logical unit at the outputs 9.1.t, 9.2.t, ... , 9.nt - on te by smallness the level value. So, if the signals are logical

units at the outputs of 9.1.2, 9.2.t, 9.p.1, this means that the smallest value of the level is stored in register 7.n, and in register 7.2 - t-e the level value is small.

Based on the position that the probability of registering a distorted symbol is greater, the smaller the absolute value of the voltage level at the output of the binary signals receiver, the algorithm for priority analysis of characters in the error polynomial formation unit (BFPO) is selected by analyzing the code combination symbols whose levels are closest to to zero. Thus, in the above example, the last character of the code combination should be placed in the first row of the memory matrix of the BFFS, the first character should be placed in the second row, and the second character should be placed in the tth row. To write information into the memory matrix of the BFPO in this sequence, it is necessary that the control pulses from the formers 15 enter the buffer storage in the same sequence.

In this example, the signals of the logical unit occur at the inputs of the elements 14.1.p, 14.2.1, ..., 14.t.2. The clock pulse from the last output of the distributor 3 through the delay block 8 overturns the trigger 10, the signal of the logical unit from the direct output of which is fed to the input of the element 11. The clock pulses through the element 11 of 11 is fed to the input of the distributor 12 of pulses, the first clock pulse appears the first output of the distributor 12, and consequently, at the second inputs of the AND 14 elements of the first row of the matrix 13. Since in this case, in the first row of the matrix 13, the signal of a logical unit is present only at the input of the AND 14.1.p element, the impulse c from the first output of the distributor 12 generates a signal of a logical unit at the output of the element 14.1.p that acts on the n-th shaper 15, the signal from the output of which indicates that the n-th character code should be written to the first line of the memory matrix message combinations. The clock pulse, which forms the second character of the subsequent code combination, is fed to the second output of the distributor 12 pulses, which leads to the appearance of a signal

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logical unit at the output of one of the elements And 14.2.1 of the second row of the matrix 13. This signal acts on the first driver 15, which leads to the recording of the first character of the message code combination in the second row of the memory matrix of the TFPE. A voltage pulse from the t-ro output of the pulse distributor 12 generates a signal of a logical unit that records the second character of the message code pattern in the tth row of the memory matrix of the TFSE. Since txn, then 5 the information is written into the memory matrix of the BFPO before the memory block 6 is filled with the values of the symbols of the following code combination. The voltage pulse from the last output of the distributor 12 through the delay block 16 is fed to the input of the trigger 10, tilting it and closing the element 11. The device is again ready to analyze the next code 5 combination.

Figure 2 shows the functional block diagram of Comparison 9 for Case and.

The values of the character levels of the code Q message combination stored in binary form, s registers 7.1-7.6, are compared with each other. For this value, the levels of characters in pairs are fed to the inputs of the selection elements of a larger number. 5 If in such elements 17 31 to the first (left) inputs to submit the number A, and to the second inputs (right) - the number B, then at their outputs there will be a logical unit signal provided. Otherwise, a logical zero occurs at the output. Elements 17-21 compare the level values of the first character with the level values of all other characters. Elements 22-25 compare the levels of the second symbol with the levels of the third, and so on. characters. The result of comparing the level of the second symbol with the first one is the inversion (element NO 32) of the result of comparing the level of the first character with the second in element 21. The results of comparing the level of the first character of the combination with the levels of the remaining 5 characters are fed to the inputs of the decoder 47, the results of comparing the level of the second character with the levels of the remaining characters - to the inputs of the decipher0

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Torah 8, etc. The number of logical units at the inputs of the decoders 7–52 Determines the location of each character in the sequence of reception accuracy. If at the inputs of any of the decoders 7 - 52 there are | only logical zeros, then this means

It means that the reliability of reception of the corresponding symbol is itself small. A more reliable character is a symbol whose comparison result contains one logical unit. The highest is the reliability of the symbol for which the result of the comparison contains all units. Since only the t least reliable symbols (in this case) are of interest, then the number of outputs of each of the decoders A - 52 is equal to t.

The application of the proposed device allows to increase the reliability of the Reception of code combinations of the message, since in the channels with fading the Overflow Counter is overflowed, which leads to the prohibition of error analysis in the code Combination.

invention formula

An error correction device (containing a linear unit whose input is an information input

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Pulse distributors pulse formers 7, blocks of a block, comparison block, block of elements I, a trigger and element of I are introduced, the first in which is combined with the control house of the analog-digital converter, the input of the first pulse distributor and the output of the analog - a digital converter is connected to the formation inputs of the first memory block, the outputs of which are connected by the same information inputs of the second memory block, the outputs of which are connected to the same inputs of the comparison block, the outputs of which are connected the corresponding output inputs of the I block, the strokes of the first impedance distributor are connected to the same control inputs of the first memory block, and the output of the first delay block is connected respectively to the last output of the first distributor and to the control inputs of the second memory block and the installation input to trigger, the trigger output is connected by the second input of the element I, the output is connected to the input of the second p pulse limiter, the outputs of which are connected to the corresponding second inputs of the block of elements whose outputs are connected to input d mi homonymous formers them

devices, the output of a linear unit of pulses, the outputs of which are

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pulse distributors, pulse formers7, delay blocks, comparison block, AND block, trigger and AND element, the first input of which is combined with the control input of the analog-digital converter, the input of the first pulse distributor and the control input of the device, the digital converter is connected to the information inputs of the first memory block, the outputs of which are connected to the information inputs of the same second memory block, the outputs of which are connected to the inputs of the same name the comparison unit, the outputs of which are connected to the corresponding first inputs of the AND block, the outputs of the first pulse distributor are connected to the control inputs of the first memory block of the same name, the EQUAL and the output of the first delay block are connected respectively to the last output of the first pulse distributor and to the control inputs of the second block the memory and the setup input into 1 trigger, the trigger output is connected to the second input of the element I, the output of which is connected to the input of the second pulse distributor, the outputs of which are soy dinenes with the corresponding second inputs of the AND block, whose outputs are connected to the inputs of the same name shapers named after 5 pulses, the outputs of which are

A dinene with information input of an analog-digital converter, the first and second memory blocks, characterized in that, in order to increase the reliability of the device, into it

the device outputs, the input and output of the second delay unit are connected respectively to the last output of the second pulse distributor and the installation input to the 0th trigger.

Claims (3)

the claims are introduced pulse distributors, pulse shapers, blocks, delays, comparison unit, block of elements And, trigger and element And, the first input 5 of which is combined with the control input of the analog-to-digital converter, the input of the first pulse distributor and is the control input of the device, the output of the analog-to-digital converter is connected to the information inputs of the first memory block, the outputs of which are connected to the same information inputs _{> 5 of the} second memory block, the outputs of which are connected with similar inputs of the comparator, outputs of which are connected to respective first inputs of the AND block you ₂ θ moves the first pulse distributor oedineny with similar delay control inputs of the first memory block, the first input and output unit connected respectively to the latter 25 to the output of the first pulse distributor and to the control inputs of the second memory block and the setting input of 1 trigger, the output of the trigger is connected to the second input of the And element, the output of which is connected to the input of the second pulse distributor, the outputs of which are an error correction device containing a linear block whose input is is the information input of the device, the output of the linear block is connected to the information input of the analog-to-digital converter, the first and second memory blocks, which is due to the fact that, in order to increase the device, in which it is connected to the corresponding second inputs of the block of elements And, the outputs of which are connected to the inputs of the same pulse shapers, the outputs of which are the outputs of the device, the input and output of the second delay unit are connected respectively to the last output of the second pulse distributor and the input of the installation in 0 “trigger. 15 * 17081 F L ♦ ► 2J 437 " -t-φ24 w * 9.1.1 * 9.1.2 9.2.1 * 9.2.2 * 9.2.3 ψ Ε 3kJc * 9.3.1 - * 9.32 ^ 9.3.3 Sai 3d * 9.4.1 50 * 9.4.2 * 9.4.3 - * 9.51 51 * 9.52 ^ 9.5.3 g - * 9.6.1 * 9.6.2 - * 9.6.3