SU1533012A1 - Device for transmission of signals of initial synchronization - Google Patents

Abstract

The invention relates to a technique for transmitting discrete information over communication channels. The purpose of the invention is to improve the accuracy of the formation of the initial synchronization signals by eliminating the phase uncertainty of the clock synchronization signal. The device contains a sensor 1 signal "point", al-OR 6, shift register 7, the adder 8 modulo two. The goal is achieved by introducing a pulse counter 2, a trigger 3, an HE 4 element and a pulse generator 5, with the help of which a recurrent sequence signal is generated at the output of the device. Given scheme shaper 5. 3 Il.

Description

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The invention relates to a technique for transmitting discrete information via communication channels and can be used in session equipment for generating signals. Start of messages.

The aim of the invention is to improve the accuracy of forming the initial synchronization signals by eliminating the phase uncertainty of the clock synchronization signal.

Figure 1 shows the structural electrical circuit of the device for transmitting initial synchronization signals; 2 shows a pulse shaper, an embodiment; FIG. 3 are timing diagrams explaining the operation of the device.

The device for transmitting the initial synchronization signals contains a sensor 1 point signals, a pulse counter 2, a trigger 3, a HE 4 element, a shaper 5 impuses, an OR 6 element, a shift register 7 shift h modulo two, and the pomirovat5 contains a э epement AND -IIF °, inverters 10 and 11, the register 12 and the capacitor 13.

The device for transmitting the initial synchronization signals operates as follows.

In the initial state at the output of the sensor 1 (Fig. Zl) there is no pulse and the trigger 3 is in the initial state. We will take the output (fig.Sv) and the first input of the element OR 6 with the presence of zero signal level at the ET.

At the R-input of the counter 2 pulses, there is a single signal level (Fig. 3b), which keeps it in the initial state. At the output of the pulse counter 2, there is a zero signal level (Fig. 3g), which enters the silt of the grigger 3, while on the BXI there are dyes of the HF element. 4 and pulse shaper. At the entrance of the element Hp; 4 there is a single signal level (fig.Zd), which keeps the

rgr 7 hzvig in the initial state at the R input. At the outputs of the reg-st i 7 shift there are zero signal levels (fig.Zh, s, and, k), which, entering the inputs of the adder 8 modulo two, set at its output zero level signal (fig.zp), which steps to the second input is an element OR b, and its output is set to a zero signal level.

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At the R-input of the counter 2 they are. sets the signal to zero. At the same time, pulses are received from the output of sensor 1 (Fig. 3a), the follow-up period of which is T,. The counting of the counter 2 pulses and the trigger 3, which is a divisor by two, is started. At the output of trigger 3 (Fig. 3b), at the output of the element OR 6, which is the output of the device, pulses appear, the follow-up period of which is Tg. The combination of these pulses is a clock signal of this device, the duration of which is determined by the counting factor of the counter 2 pulses.

During the entire counting time of the counter 2 pulses at its output and at the output of the element NO 4 (Fig. 3 d, e), the signal level does not change, therefore, the shift register 7 is kept in the initial state.

After counting a predetermined number of pulses, a counter 2 pulses at its output establishes a single signal level (Fig. 3g), which is fed to the R-input of the trigger 3 and to the inputs of the HE element 4 and the driver 5 pulses.

The trigger 3 is reset, and the pulses at the output of the device are stopped. At the output of the element HF 4 and at the R input of the shift register 7, a zero signal level is set to enable the shift register 7 to operate. When the state changes at the input of the imaging unit 5 from zero to one at its output (Fig. 3e) and at the RS input of the shift register 7, a pulse appears that sets the shift register 7 to the state at which (k-1) - The output of the shift register 7 (Fig. 3) is set to a single signal level. This state of the shift register 7 is maintained until the pulse appears at its C input.

When this pulse arrives at the k-th output of the shift register 7 (fig.Zi) and at the corresponding input of the adder 8, modulo two establishes a single level, which through the OR 6 element arrives at the device output and at the V-input of the shift register 7. Thus, the device begins to receive a signal of a recurrent sequence.

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In order to set the device to the initial state, a single signal is again fed to the R input of the meter 2 pulses and gf is shortened to the arrival of a sequence of pulses T from the output of sensor 1.

The pulse counter 2 is reset, and at its output a zero level is set, which is fed to the R input of the trigger 3 and to the inputs of the HE element 4 and the driver 5. The output of the cell is NOT set to a single signal level that sets the shift register 7 to the initial state and keeps it until the signal level changes to zero.

At the output of the shift register 7, zero values of the signal are set. At the output of the adder 8 modulo two and at the output of the OR element 6, the signal level is set to zero (Fig. 3). The device is again in the initial state.

Claims (1)

Invention Formula A device for transmitting initial synchronization signals, comprising 0 thirty five five 0 126 the shift register, whose output bits are connected to the inputs of the modulo two adder, as well as the point signal sensor and the OR element, is enough to increase the accuracy of the initial synchronization signals by eliminating the phase uncertainty of the signal clock synchronization, a pulse counter, a pulse shaper, a trigger and a NOT element are entered, the pulse counter output is connected to the V-input of the pulse counter, to the R-trigger input and to the inputs of the pulse shaper and the NE element, the output of which is It is connected to the R-input of the shift register, to the RS-input of which the output of the pulse former is connected, and the output of the modulo-two adder and direct output of the trigger through the OR element is connected to the V-input of the shift register, whose C-input is combined with the corresponding trigger inputs and pulse counter and is connected to the sensor output point of signals, and the inverse trigger output is connected to the D-input trigger. P5L Output 10RM put. 2 A / piece sync Signal Duration. Signal RP Fig, s