SU1524045A1 - Four-input single-bit adder - Google Patents

Abstract

The invention relates to computing and can be used in the construction of multi-operand arithmetic devices, in particular, high-speed multipliers. The aim of the invention is to reduce the volume of equipment. A four-input adder containing AND 5-10 elements, NOT 1-4 elements, OR-NOT 12 element and modulo-two adder 11 generates a sum value and a two-digit transfer code. 1 il.

Description

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The invention relates to computing and can be used to build multi-operative arithmetic devices, in particular when constructing high-speed multipliers.

The purpose of the invention is to reduce the amount of equipment.

The drawing shows a schematic diagram of a four-input single-bit adder.

The four-input single-digit adder contains the elements NOT, the AND 5-10 elements, the modulo-11 adder two, the IL-NOT-12 element, the inputs of 13 operands, the output of the 14 sum, the output of the 15th least significant transfer and the output of the 16th most significant transfer .

The four-input one-bit adder operates as follows.

At output 1A, a value of sum C is formed, equal to one, when the number of units at the inputs of the modulo two is equal to one or three,

At outputs 15 and 16, a two-digit transfer code is generated. The value of the lower bit of the transfer P is determined by the function P ABED + AVE5 - fflSED +

. + ABED + ABED + AVEEO. The value of the second discharge of the transfer Pg at the output 16 is equal to one, when the inputs of the element And 5 will be four units, i.e. P ABED.

Claims (1)

Invention Formula A four-input single-bit adder containing six elements AND, an adder for 1 MODULE two and four elements NOT, and the inputs of the elements are NOT connected respectively to the inputs of the first, second, third and fourth operands of the four-input single-digit adder, the inputs of the first And element are connected respectively to the inputs the first, second, third and fourth elements are NOT, the first and second inputs of the second element And are connected respectively to the output of the first and to the input of the second element NOT, the first and second inputs of the third element And are connected respectively to the input of the first and to the output of the second element NOT, the first and second inputs of the fourth element And the connection with the output of the second and with the input of the third element NOT, the first and second inputs of the fifth element I are connected respectively to the output of the first and to the input of the fourth element NOT, the first input of the sixth element I is connected to the output of the first element This is NOT; Modulo two inputs are connected to the inputs of the first, second, third, and fourth elements, respectively; modulo two output is connected to the output of the sum of a four-input single-bit adder; the output of the first element I is connected to the output of the higher discharge of the transfer of a four-input single-bit accumulator, characterized in that, in order to reduce the volume of equipment, the four-input single-digit accumulator additionally contains an OR-NOT element, the third and fourth inputs of the second and third elements And connected to the outputs of the third and fourth elements NOT, the third and fourth inputs of the fourth element And connected to the outputs of the first and fourth elements NOT, the third and fourth inputs of the fifth element And connected to the outputs of the second and third elements NOT, inputs from the second to the fourth, the sixth zleenite And connected to the outputs of the second, third and fourth elements NOT, the outputs of the elements And, from the first to the sixth, are connected to the corresponding inputs of the element OR NOT, the output of which is connected to the output of the lower bit of the transfer four input one-bit adder.