SU1509957A1 - Device for selecting indicators of object images - Google Patents

Abstract

The invention relates to automation and computer technology and can be used in preprocessing devices in image processing and recognition systems. The aim of the invention is to improve the accuracy in image processing, which is achieved by forming new features when analyzing a part of an image defined by two adjacent rows. 1 il.

Description

The invention relates to automation and computing, in particular, to devices for selecting features of image objects.

The purpose of the invention is to increase the accuracy of determining the number of attributes to be implemented.

The drawing shows the block diagram of the device.

The device contains the first 1 and second 2 registers, the first 3, the second 4 and the third 5 triggers, the first 6, 7, the second 8, 9, the third 10, the fourth 11 and the fifth 12, 13. and 14 groups of elements I, the first 15 and the second 16 decoders, the first 17, the second 18, the third 19, the fourth 20, the fifth 21 and the sixth 22 elements And, a group of flip-flops 23 -and 24, the first 25, the second 26, the third 27, the fourth 28 and the fifth fifth elements OR, the first 30 and second 31 inverters, first 32 and second 33 counters, first 34, second 35, third 36, fourth 37, fifth 38, sixth 39 and: seventh 40 delay elements.

The diagram shows the first 4l and second 42 informational inputs of the device, the input 43 synchronizes the 1st device, as well as the first 44 and second 45 informational outputs of the device.

The device works as follows.

Before starting work, all its elements and components are set to their original state.

In register 1, the first line of the image is entered in the information bus from the input 41 by the sync pulse from input 43. The same clock pulse in register 2 uses the information bus from input 42 to enter the code of the second line of the image. The same sync pulse arrives at the unit input of trigger 3, setting it in a single state, in which it has a high potential from a single dispatch

eaten k |

move opens element 19 for potential input.

The state of the registers 1 and 2 is decrypted by the decoders 15 and 16, respectively, which are connected to the information. register outputs so that they implement only the zero function of the values of their bits, generating a high potential at the output.

High potentials from the outputs of the decoders 15 and 16 arrive at the potential inputs of the element And 18, opening it at the potential inputs. The outputs of the decoders 1 and 16 are inverted by inverters 30 and 31, respectively.

At a low potential at the output of one of the decoders, a high potential from the output of the corresponding inverter goes through the element OR 29 to one potential input of AND 6–9 elements, the other potential inputs of which are connected to the forward or inverse high-order output of the corresponding register.

To obtain the zero function of the values of the bits of registers 1 and 2, their contents are shifted to the left by one bit after analyzing the higher bit for which the pulse from the output of the OR 25 element, the delayed element 35 to the response time of the registers 1 and 2 and the decoders 15 and 16, executes , the unit inputs of the flip-flops 23 and 24, through the elements 6 and 8, respectively, receive the unit values of the higher-order codes of registers 1 and 2, setting them to a single state.

By the same impulse, the zero inputs of the flip-flops 23 and 24, through the elements 7 and 9, respectively, receive the zero values of the codes of the higher bits of registers 1 and 2, resetting them to the zero state.

A high potential from a single output of the trigger 23 enters the first potential inputs of the elements 13 and 14, and a high potential from the inverse output of the trigger 23 enters the first potential inputs of the ale. cops and 12 and 22.

The high potential from the single output of the trigger 24 goes to the second potential inputs of the elements 12 and 14, and the high potential from the inversion output of the threshra 24 goes to

0

five

0

five

0

five

0

five

0

the second potential inputs of the elements And 13 and 22.

A pulse from the output of the element OR 25, the delayed element 36 for the response time of the flip-flops 23 and 24, opens one of the elements 1214 and 22.

With a zero value of the high bits of both registers, the flip-flops 23 and 24 remain in the initial state. A high potential from the inverse outputs of these flip-flops opens an AND 22 element at the potential input, to the pulse input of which a pulse is output from the output of the delay element 36.

This impulse, passed through element 22, arrives at a single input of trigger 5 and sets it to a single state in which it opens a potential from element output 21 and potential element 21, at the impulse input of which impulses from the output of delay element 37.

The pulse from the output of the delay element 37, passed the element And 21, and then the element OR 28, is fed to the counting input of the counter 33 and to the pulse input of the element And 19, opened in the potential input by a high potential from the single output of the trigger 3.

; The pulse from the output of the element 19, delayed by the element 34 for the duration of the operation of the counter 33, arrives at the clock inputs of the registers 1 and 2 and shifts their contents one digit to the left. By the same impulse from the output of the element OR 25, the delayed element 35 for the response times of registers 1 and 2 and decoders

15 and 16, the analysis of the obtained new values of the high register bits is allowed.

With each subsequent analysis of the zero values of the high bits of both registers, the described operation cycle of the device is repeated. At the same time, with each new cycle, the contents of counter 33 increase by one.

With the appearance in the higher bits of registers 1 and 2 of single values, one of the elements 12, 14 opens. Suppose, for definiteness, that an AND 14 element is opened, corresponding to a single value of the higher bits of both registers, and therefore to a single value of their flip-flops 23 and 24.

The impulse from the output of the element And 14, having passed the element OR 26, goes to the single input of the trigger 4, sets it to the single state, and through the element OR 27 to the zero input of the trigger 5, resetting it to the zero state.

A high potential from the single output of the trigger 4 opens the element AND 20 at the potential input, the pulse input of which receives a pulse from the output of the delay element 37.

This impulse, passed the element AND 20 and then the element OR 28, is fed to the counting input of the counter 33 and

509957 "

From the output of the elements And 20 and 21, the pulse arrives, having passed the element OR 28, to the counting input of the counter 33 and to the pulse input of the element And 19.

From the output of the element AND 17, the pulse after the delay by the element 38 for the duration of the operation of the counter 32 enters the zero input of trigger 4 and through the element OR 27 to the zero input of trigger 5, resetting them to the zero state and thus completing the process of analyzing the elements of one sign .

After shifting the contents of registers 1 and 2 by one bit to the left, new values of their higher bits are obtained, and the analysis process continues with which the counter 32 counts-j

ten

15

the pulse input element and 19, opens the number of viewed signs

Moreover, the potential input has a high potential from a single trigger output 3.

From the output of the element AND 19, the pulse after the delay by the element 34 again arrives at the clock inputs of registers 1 and 2 to shift their contents one bit to the left, after which the next new analysis of the obtained new values of the higher bits of registers 1 and 2 begins.

The sequential process of shift and analysis goes as long as in the higher bits of both registers there are no more zeros in the mc.

Then, the triggers 23 and 24 are reset to their initial state, and both potential inputs of the And 22 element are opened from their inverse outputs with a high potential.

The impulse from the output of the delay element 36, having passed the element 22, arrives at the single input of the trigger 5 and sets it to the single state. The high potentials from the direct outputs of the flip-flops 4 and 5 open both potential inputs of the element And 17, and the high potential from the direct output of the trigger 5 opens the element And 21 at the potential input. Then the impulse from the output of the delay element 37 passes the electrical signals And 17, 20 and 21.

From the output of the element And 17 pulse arrives at the counting input of the counter. 32, fixing the end of the analysis of the elements of the current attribute and calculating the total number of signs to be performed.

five

0

five

0

five

0

five

parts of the image defined by two adjacent rows, and the counter 33 counts the length of the analyzed part of the image in discrete increments.

The analysis process continues until both registers are reset to the zero state after the next shift. The obtained zero functions of registers 1 and 2 are implemented by decoder 15 and 16, respectively.

High potentials from the outputs of the decoders 15 and 16 open both potential inputs of the element I 18, to the pulse input of which impulses come from the output of the element 37 of the delay. At the same time, the low potential from the outputs of the inverters 30 and 31 through the OR element 29 closes the AND 6-9 elements by one potential input, blocking the process of analyzing the higher bits of the registers 1 and 2.

From the output of the element And 18, the pulse arrives at the zero input of the trigger 3, resetting it to the zero state. Then the low potential from the direct output of the trigger 3 is closed by element II 19 at the potential input, blocking the shift of the registers 1 and 2.

The same pulse through the element 39 of the delay is supplied to the pulse inputs of the elements And groups 10 and 11, allowing the census of the contents of the counters 32 and 33 at the output 44 and 45 of the device, respectively. At the same time, the number of all viewed features of a part of the image from two adjacent lines is rewritten to the output 44 of the device, and the output 45 to rewrite

the number of all viewed pairs, representing information about the length of the part of the image specified by its two adjacent rows.

After a census of the contents of counters 32 and 33 at output A4 and 45 of the device, respectively, with the same pulse delayed by the delay element 40 for census time, counters 32 and 33 are reset.

 After that, the device is ready for a new work cycle.

Claims (1)

Invention Formula A device for selecting features of an image of objects, containing a first register, the information input of which is the first information input of the device, the synchronization input is the synchronization input of the device, the clock input is connected to the output of the first delay element, the forward and inverse outputs of the higher resolution yes first register; connected to one of the inputs of the corresponding elements AND of the first group, the first element OR, one input of which is connected to the synchronization input of the device, the other connected to the outputs of the first delay element, and the output connected to the inputs of the second and third delay elements, the second register, whose information input is The second information input of the device, the synchronization input is connected to the synchronization input of the device, the clock input is connected to the output of the first delay element, the forward and reverse outputs are st The second bit of the second register is connected to one input of the corresponding elements AND of the second group, a group of triggers, the single and zero inputs of which are connected to the outputs of the corresponding elements AND of the first and second groups, the first counter, the counting input of which is connected to the output of the first AND element, and the information outputs connected to the same inputs of the elements of the third group, whose outputs are the first information output of the device, the second counter, the information outputs of which are connected to the same inputs of the elements And even the second group, the outputs of which are the second information output device, decoders, inverters, the second and third elements And the second, third and fourth elements OR, characterized in that, in order to improve the accuracy of the device, it introduced the first trigger, a single input of which is connected to the sync input of the device, the zero input is connected to the output of the second element I, and, the direct output of the first trigger is connected to one input of the third element I, the output of which is connected to the input the first delay element, the fifth group of elements And, the inputs of which are connected to the corresponding direct and inverse outputs of the trigger group and with the output of the third delay element, and the outputs are connected to the inputs of the second element OR, the fourth delay element whose input is connected to the output of the third delay element and the output is connected to one the inputs of the first and second elements are AND, the second trigger, whose single input is connected to the output of the second element OR, and the direct output is connected to another input of the first element And, the fifth delay element, the input of which is connected to the output of the first element AND, and, the output is connected to the zero input of the second trigger and to one input of the third OR element, the other input of which is connected to the output of the second RSHI element, a quarter element. And, whose inputs are connected to the direct output of the second trigger and the output of the fourth delay element, and the output is connected to one input of the fourth OR element, the output of which is connected to the counting input of the second counter and to the other input of the third And element, the sixth delay element whose input is connected to the output of the second element And, and the output is connected to the synchronizing inputs of the elements, And the third and fourth groups, the fifth element And, one input of which is connected to the output of the fourth element delay, and the output is connected to another input of the fourth OR element, the seventh delay element, whose input is connected to the output of the sixth delay element, and the output is connected to zero inputs of counters, the sixth element And, the inputs of which are connected to the inverse outputs of the trigger group and to the output of the third element W five