SU1501086A1 - Device for determining correlation function - Google Patents

Abstract

The invention relates to specialized computer aids and is intended to find estimates for the correlation function of random processes. The aim of the invention is to increase the speed of calculating the correlation function and simplify the device. The device contains a controlled amplifier 1, an amplifier 2, a switch 3, an analog-to-digital converter (A / D converter) 4, a digital-to-analog converter (D / A converter) 5, an adder 6, a register 7, a memory block 8, a control block 9. The essence of the invention is that the information input of the DAC 5 is connected to the output of the A / D converter 4, and the output controls the amplifier of the first process by a signal proportional to the delayed signal from the output of the amplifier of the second process. This eliminates the hardware multiplication of the ordinates of the first and second processes. The resulting signal, proportional to the product of these quantities, is converted by the ADC and fed through an adder to a memory block, the output of which, after averaging, is the estimate of the correlation function. 1 hp f-ly, 2 ill.

Description

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The invention relates to specialized computing equipment and is intended to find the correlation function of random processes, for example, using sensors that convert physical veins into an electrical signal.

The purpose of the invention is to increase the speed and simplify the device.

FIG. 1 shows a block diagram of the device; in fig. 2 - block diagram block diagram.

The device contains a controlled-amplifier 1, amplifier 2, switch 3, analog-to-digital converter (A1SC) 4, digital-to-analog converter (PAI) 55 adder 6, register 7, memory block 8, control block 9, first 10 and second 11 inputs , information output 12, output 3 of the ordinate number and exit 14 of the termination of the calculation of the ordinate.

The control unit 9 (FIG. 2) constitutes a clock pulse generator 15, a trigger 16, elements AND 17 and 18, an element OR 19, elements AND 20-22, an element AND 23, an element OR 24, - an element AND 25, an element OR 26, single pulse generator 27, trigger 28, counter 29, element OR — NOT 30, element 3.1, trigger 32, element I 33, counters 34 and 35, element 36 and 36, second element NOT 37, element 38, trigger 39 as well as the eighth 40, the ninth 41, the fourth 42, the third 43, the fifth 44, the first 45, the seventh 46, the second 47, the sixth 48, ten of the 49 and eleven 50 outputs.

The device works as follows.

The first 10 and second 11 inputs of the correlator receive signals X (t) and y (t), respectively. At the beginning of the cycle for determining the correlation function, switch 3 connects amplifier 2 to input AIJ, n 4, the number M of which bits depends on the requirements for measuring accuracy. Consider the case of using an eight-bit ADC with a bit-wise conversion. When a start signal appears, the ADC at output 47 of the ADC synchronization unit in 8 cycles performs the operation of converting digital cnrHaj a y (t). This code is from the output of A1SC

0

0

five

0 5 0

with

0

em pa ip (1 normal DAP 5 input and signal) (rob ro DAC pa output 41 of control unit 9 is entered into DAC. After conversion, amplifier 1 is controlled by voltage from output 11AL 5, proportional to signal of amplifier 2, delayed by time A t, set synchronization unit.

After switching switch 3 on the signal at output 46 of block 9, the signal from amplifier 1 of the first process

proportional to the product X (t) it Y (), is fed to the ATSL 4 input and, after being converted to digital form, is fed to the input of the adder 6. Since the inverse control input of the register 7 from the output 49 of block 9 receives a low level signal Reset the register, then the input of the adder 6 receives the zero code and the code at the output of the adder is equal to the ADC 4 code. The presence of recording resolution signals Recording and Selecting a chip, respectively, at outputs 42 and 44 of control unit 9 ensures that this code is written into the memory block 8 at the address set at output 48 b eye control, after which the address value is incremented by one. A1SC 4 performs the next conversion cycle, and next. the memory cell of the memory block 8 is written down a code proportional to the value of X (t) y (t + 2A t), i.e. second point of correlation function. After writing the values of N points to the memory block 8, the measurement cycle of the correlation function is repeated, but the reading signals on the control unit outputs 43 and 44 store the code stored in the memory cell at the current address to the input of the register 7 and entered into it by the Strobe register signal at the output 45 of the control unit, then it goes to the input of the adder b each cell records the sum of the current value and value on the previous cycle of measuring the i-th point of the correlation function. I -

Thus, there is an accumulation of K values of the ordinates of the correlation function in order to obtain an average value in accordance with the formula

. k Heap (s) i Xx (t) .y (t - (- iA),

from 1 1

To enter the values of the correlation function points on the last measurement cycle, the address change is accompanied by a signal at the eleventh output 50 5 of the control unit 9 and, accordingly, at the output 1-4 of the device.

The control unit 9 (FIG. 2) operates as follows.

The generator 27 of a single pulse 10 sets the first 29, second 34 and third 35 counters and D-flip-flops 16, 28 and 39 to zero. The third trigger 32 is set to one. The first element 15 NOT 31 is intended to generate a counter reset signal. At the inverse output of the first element OR-NOT 30, a single signal appears.

The first pulse from the generator of 15 clock pulses translates the first trigger 16 into one state, allowing the passage of clock pulses 25 through the first element 17 and the first element OR 19 to the input of the first counter 29 with a conversion factor of eleven. Thus, a delay of 30 clock cycles is performed, which is necessary for switching the correlator switch 3. Signal Starting AMS at output 47 of the control unit is two cycles long. On the rear signal. Start ADC start-35 Code from the output of the adder 6 in. corresponding to the ADC 4 correlator. During cycles 3-8, signals are read at the output of the second element OR 24 and the chip is selected at the output of the third element OR 26, which from output 43 and control module 44 output go to the write enable inputs of memory block 8. However, the contents of the memory location in the register 7 will not be written until the output of the synchronization unit 49 has a low level signal, i.e. the fourth trigger 39 is in the zero state.

During cycles 3–10, analog-to-digital conversion of the A / D converter 4 takes place, to the input of which switch 3 supplies the signal of amplifier 2 of the second process (the control signal of the switch at output 46 of the synchronization unit is zero). Received at the output of the A / D converter 4, the code z.anosits in the DAC 5 according to the signal of the Strobe D / A converter, which is formed on the eleventh clock pulse treg

40

with the address set at output 48 of the control unit. The input of the adder 6 still does not receive information from register 7, because the signal Reset register has a zero value.

After the end of the recording in the next cell of the & 8 memory, the content of the second counter 34 is increased by 45 per unit, which corresponds to the setting of the address of the next cell of the memory block 8. This operation sequence is repeated until the second counter 34 is completely filled. The conversion factor of this counter is equal to the number of cells of block 8. memory, which corresponds to the number of points of the calculated correlation function.

When the second counter 34 overflows, the second trigger 28 is set to the zero state, as a result of which a calculation cycle of the mutual correlation function is prepared

5d

55

the dark element AND 20 and the fourth element P1 21. The signal from the output of the first element AND 23 after the eleventh clock symbol sets the second trigger 28 to the one state that ensures the passage of clock pulses to the input of the first counter 29 without delay through the second element And 18 and the first element OR 19, as well as the appearance of a single switching signal of switch 3. Thus, an amplifier 1 controlled by the output of DAL 5 is connected to the input of ADC 4 proportional to the ordinate of the second process, delayed by the required time. m A S.

The next clock pulse resets the outputs of the first counter. 29, which leads to the appearance of a pulse. The ADC starts at the inverse output of the first element OR NOT 30 and sets the third trigger 32 to the zero state, allowing the passage of pulses through the seventh element 33 to the input of the second counter 34

The subsequent series of clock pulses provides signal-digital conversion of the signal of amplifier 2 in the described order, but instead of the DAC strobe signal, the control unit generates a Record signal at the output of the fifth element And 22, which allows writing to memory B of the block

0

with the address set at output 48 of the control unit. The input of the adder 6 still does not receive information from register 7, because the signal Reset register has a zero value.

After the end of the recording in the next cell of the & 8 memory, the content of the second counter 34 is increased by 5 per unit, which corresponds to the setting of the address of the next cell of the memory block 8. This operation sequence is repeated until the second counter 34 is completely filled. The conversion factor of this counter is equal to the number of cells of block 8. memory, which corresponds to the number of points of the calculated correlation function.

When the second counter 34 overflows, the second trigger 28 is set to the zero state, as a result of which a calculation cycle of the mutual correlation function is prepared

d

five

the next implementation of random processes arriving at inputs 10 and 11 of the correlator. At the same time, the content of the third counter 35 is increased by one, and the signal at the output of the second element HE 37 sets the quarter trigger 39 to one, which leads to the removal of the low level signal. The register is reset from the control input of the register 7. Therefore, in each the memory cell accumulates the sum of the values of the corresponding points of the correlation function, since the input of the adder 6 is written to the register 7 by the ° strobe signal generated by the output of the sixth element And 25 the content code corresponds to uyuschey memory cell at (i-l) -M measuring cycle and the other input - output current code A1SCH 4

The third counter 35 serves to count the number K of averaged measurements of the correlation function and has a corresponding conversion factor. When this counter is filled at the output of the eighth element AND 36, a signal appears allowing the passage through the ninth element 38 of the output gate signal, which is used to gate the output of the device's output to the outputs 1 2 and 1 3.

formula of invention

Claims (1)

1. An apparatus for determining a correlation function comprising an analog-to-digital converter, a switch, a register, an adder, a memory unit and a control unit, wherein the recording enable input and the register output are connected respectively to the first output of the control unit, to the first input adder, the second input of which is connected to the output of analog-to-digital. The converter whose start input is connected to the second output of the control unit, the output of the adder is connected to the information input of the memory unit, the read enable input, the first and second write enable inputs and the address input of which are connected to the third to sixth outputs of the control unit , the output of the memory block was informational, “another output of the device, about 10 of which, in order to Q 5 0 5 o five Jq gp five speed and simplification, the device contains a digital-to-analog converter, an amplifier and a controlled amplifier, the information input of the controlled amplifier and the amplifier input are the first and second information inputs of the device, the outputs of the controlled amplifier and amplifier are connected respectively to the first and the second infermentation inputs of the switch, the output and control input of which are connected respectively to the information input (| analog input of the analog-digital converter and the seventh output The control unit, the eighth, ninth and tenth outputs of which are connected respectively to the clock input of the analog-digital converter, the clock input of the digital-to-analog converter and the reset input of the register, the output of the analog-digital converter is connected to the information input of the digital-analog converter, the output of which is connected to the set input the gain of the controlled amplifier, the input of the memory unit is connected to the information input of the register, the sixth and eleventh outputs of the control unit are responsibly by the output of the ordinate number and the output of the termination of the device's ordinate. 2 "Device according to claim 1, characterized in that the control unit comprises a clock pulse generator, a single pulse generator, eight AND elements, three OR elements, four triggers, two counters, two NOT elements, an element; OR-NOT, and the generator output clock pulses connected to the clock input of the first trigger, the first inputs of the first and second elements And is the eighth output of the block, the direct output of the first trigger is connected to the second input of the first element And, the third input of which is connected to the information input of the first three gagera, the first input of the third element. And the inverse output of the second trigger, the direct output of which is connected to the second input of the second element AND, the first input of the fourth element AND, is the seventh output of the block, the UXILE OF the first element AND is connected to the first input of the first 9 the OR element, the second input and output of which are connected respectively to the output of the second element AND and the counting input of the first counter, the first bit output of which is connected to the first inputs of the element lillH-dE and.  The fifth and sixth elements are And the second bit the output of the first counter is connected to the second inputs of the sixth element AND and the element OR NOT and the first inputs of the second element OR and the seventh element And, the second input of the second element OR is connected to the third inputs of the sixth element And and the element I.PI-NOT and the third bit output of the first counter, the fourth bit output of which is connected to the second input of the fifth element I, the clock input of the third trigger, to the second input of the seventh element And, the first input of the eighth element And and the fourth input m of the OR-NOT element whose output is the second output of the block, the output of the fifth element AND is connected to the second inputs of the third and fourth elements AND, the outputs of which are respectively the ninth and fourth outputs of the block, the inverse output of the seventh element AND in I of the second trigger, the clock input of which is connected to the overflow output of the second Counter and the counting input of the third counter, the output of the generator of a single pulse is connected to the inputs of the installation in O of the first and second and fourth triggers, input m-install 0108610 in 1 of the third trigger and through the first AND element with the installation inputs of O nepBoi o, the second and third counters, the output of the second OR element is connected to the first input of the third OR element and is the third output of the block, the output of the fourth AND element is connected to the second input 10 of the third OR element and is the fourth output of the block, the outputs of the third CRPD element and the sixth AND element are respectively the fifth and first outputs of the block, the information 15 Hbie inputs of the second, third and fourth triggers are connected to the zero potential bus, the inverse output of the third trigger is connected to the second input of the eighth element And, the output of which is connected to the first input of the ninth element And and the counting input of the second counter, the output of which is the sixth output of the block, the first discharge output of the third counter 25 is connected via the second element NOT to the installation input in VI of the fourth trigger, the output of which is the tenth output of the block; The output of which is the eleventh output of the block, the output of the replenishment of the third counter is connected to the clock input of the fourth trigger, the direct output of which is the tenth output of the block. phage. 2