SU1501023A1 - Data input device - Google Patents

Abstract

The invention relates to computing and is intended to enter information into a computer. The aim of the invention is to increase the reliability of the input information by eliminating the input of information at the moments of simultaneous pressing of several switching elements. The device contains a clock pulse generator 1, the first and second counters 2 and 9, multiplexer 3, decoder 4, switching unit 5, bounce block 6, first and second registers 7 and 10, trigger 8, comparison unit 11. This set of elements allows Do not exclude the issuance of information on the output of the device while simultaneously pressing two or more switching elements. 1 il.

Description

3150

The invention relates to computing and communication technology and is intended to enter control information.

The purpose of the invention is to increase the reliability of the input information by eliminating the input of information at the moments of simultaneous pressing of several switching elements.

The drawing shows a block diagram of the device.

The device contains 1 clock pulse generator, the first counter 2, the multiplexer 3, the decoder 4, the switching unit 5; the elements, the bounce control unit 6, the first register 7, the trigger 8, the second counter 9, the second register 10, the comparison unit 11.

The device works as follows.

From generator 1, the pulses go to counter 2, at the output of which all possible states of counter 2 are output sequentially and periodically, the number of which is equal to or greater than the number of possible switching elements of unit 5, and each of the switching elements is assigned one of the possible states line (combinations) counter 2 ..

Decoder 4 selects a subset of the states of counter 2 and outputs a sig. Nal on the corresponding tire of the block 5.

The multiplexer 3, within the selected subset of states, scans along the vertical buses of the block 5, inquiring about their condition, and in case of detection of the signal, gives it to the bounce block 6.

Block 5 of switching elements contains switching elements, the total number of which is determined by the chosen alphabet, and each element corresponds to a code unique to it. When any switching element is closed, the horizontal and vertical tires are connected in accordance with the location of the element in the switching matrix.

The debounce block 6 converts the incoming from the multiplex (aperture 3 signal into a pulse signal, the duration of which falls within the period of the generator 1.

Block 6 can be implemented in the form of a one-shot with a pulse duration equal to the period of the generator 1 clock pulses. At the same time, the cycle time for polling the switching elements must be greater than the bounce time of the open switching element. This eliminates failures when writing information to registers 7, 10, trigger 8 and counter 9. Writing into these elements is performed on the leading edge of the pulse of block 6, and when this occurs, when the primary pulse of block 6 is written, the state corresponding to the code of the pressed switching element In the first register 7, the result of the state comparison on the input and output of the register 7 is recorded simultaneously in the trigger 8.

During the entire closure of the switching element of block 5, pulses with a period equal to the interrogation cycle of all switching elements will be observed at the output of the debounce block 6, the occurrences of pulses of block 6 correspond to the state of the closed switching element of block 5. The pulses of block 6 provide recording the state of counter 2 corresponding to a closed switching element to register 7.

Comparison unit 11 provides a constant comparison of the codes at the input and output of the register 7. If the codes are the same, a zero level is formed in the output of the 1 1 srn block, indicating that the codes are equal, in other cases a single level is formed. The result of comparing codes with code. Comparison unit 11 is fed to informational input of trigger 8, to the synchronization input of which pulses are received from chattering block 6. The leading edges of pulses from block 6 are written to trigger B. Simultaneously, the leading edges of the same pulses are written to register 7 and to trigger 8 eliminates the effect of transients on the recording result, therefore, eliminates the failure for this reason.

The single state of the trigger 8 is the control of the fault reset, dp of the second counter 9, which is designed by dp of counting the pulses of the bounce block 6.

The counting of pulses by the counter 9 is carried out at the zero state of the trigger 8. If the zero state

maintained for the time required to overflow the counter 9, the latter generates a signal under the second register 10, which records the output state of the first register 7.

The counter 9, having reached the threshold value or overflow, stops until the Q signal is received as a single state from the output of the trigger 8. Such an algorithm of the counter 9 operation can be implemented using a shift register, the information input of which is J5 permanently connected to the unit level, the fault input is connected to the trigger output 8, the clock input is connected to the output of the bounce block, and the high-order output 20 of the register is the output itself.

The threshold value of the counter 9 is selected from the condition of reliable operation of the device and is 25 values of 1 or more.

Increasing the threshold value of counter 9 is limited by the need for NfciM speed. The minimum threshold value of the counter 9 of the DA is 1 when the counter 9 degenerates into a D-flip-flop.

Consider the operation of the device, when one switching element is closed. In this case, the code conditions accompanied by the issuance of pulses from block 6 will be the same and, starting from the second pulse, the comparison block 11 and the trigger 8 will fix the coincidence of codes and, accordingly, zero states on their pins.

When the threshold value of the counter is 9, exactly one, with the third pulse of the deblocking unit 6, the counter 9 outputs a signal for overwriting information using the register 10 to the device output.

When the threshold value of the counter is 9, greater than one, the information is overwritten at the output of the device with a longer time delay.

In the case if the system is simultaneously closed two or more of which are radio elements of block 5, then the code state is 35

40

45

50

five

ABOUT

0

five

0

five

1b, accompanied by the issuance of pulses from block 6, will alternate and. at the output of the comparator block II, discrepancies will be fixed in the form of single signal levels, which, rewriting into trigger 8, keeps counter 9 from triggering. Consequently, the information in register 10 is not recorded and is not transmitted to the device output.

Thus, the delivery of unreliable information to the output at the simultaneous closure (pressing) of more than one switching element is excluded.

Claims (1)

Invention Formula A device for entering information containing a clock pulse generator, the first and second counters, a trigger, a first register, a decoder, a multiplexer, a block of switching elements, the inputs of which are connected to the outputs of the deshifter, and the outputs are connected to the information inputs of the multiplexer, whose address inputs are connected to the inputs of the decoder , information inputs of the first register and outputs of the first counter, the input of which is connected to the output of the clock generator, characterized in that, in order to increase reliably These inputs, a second register, a bounce block and a comparison block are entered into the device, the inputs of the first group of which are connected to the outputs of the first counter, the inputs of the second group of the comparison block are connected to the outputs of the first register and information inputs of the second register, and the output is connected to the information input of a trigger The clock input of which is connected to the clock input of the first register, the output of the deconfiguration block and the clock input of the second counter, the control input of which is connected to the trigger output, and the output is with the clock input of the second trigger, the input of the deblocking unit is connected to the output of the multiplexer, the outputs of the second register are the outputs of the device.