SU1497721A1 - Pulse train generator - Google Patents

Abstract

The invention relates to a pulse technique. The purpose of the invention is to increase the reliability of the device. In the initial state, the device blocks are held by the signals from the direct and inverse outputs of the trigger 12, which is transferred to the working position by a signal on the Start bus of the device. The introduction of the frequency divider 13 into the device ensures the division of the pulse sequence generated by the device into a series of pulses, in each of which the value of this interpulse interval is stored. The change in the value of the interpulse interval is made at the border of the pulse train. Such an algorithm of the device operation provides (without degrading the accuracy characteristics) a reduction in the speed requirements of the device blocks, i.e. increases the reliability of the device. 1 il.

Description

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The invention relates to a pulse technique and can be used in radio engineering.

The purpose of the invention is to increase the reliability of the pulse sequence generator.

The drawing shows a structural electrical circuit of the proposed generator.

The pulse sequence generator contains a pulse generator 1, counters 2 and 3 pulses, decoders 4 AND 5, element 6, driver 7, key block 8, delay block 9, multiplication block 10, adder 11, trigger 12, frequency divider 13. The output of the pulse generator 1 is connected through a serially connected counter of 2 pulses, a decoder 4, element 6, a driver 7, a frequency divider 13, a delay unit 9, and a multiplication unit 10 connected to the synchronization input of the pulse counter 3, the output of which is connected to the inputs of the adder 11 and decoder 5, the output of the latter is connected to the first input of the installation of the trigger 12, the inverse output of which is connected to the inputs of the installation of the frequency divider 13, the counter 3 pulses and the counter 2 pulses, the control input of the latter is connected to the output of the block 8 keys, The first and second inputs of which are connected respectively to the outputs of the adder 1 1 and the former 7c. The output of the} of the 1 pulse generator is connected to the second input of the AND 6 element, the third input of which is connected to the forward output of the trigger 12, the second input of the installation of which is connected to W1N Start-up device.

The pulse sequence generator works in the following way.

From the corresponding setters (not shown), the multiplication unit 10 and the adder i 1 are continuously supplied with the code values of the parameters a and a, respectively, (where a is the linearity coefficient, n, is the initial value of the interpulse interval

the number of pulses of the pulse generator 1) i per pulse counter 3 is the sign of the direction of change of the interval (+ or -), and the frequency divider 13 is the division factor of. From the generator

1 pulses to the counting input of the counter

2 pulses are pulsed, however, in the initial state, this counter is held by the output signal.

5 0 5 0 d

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of the zeroed trigger 12 in the unit state, which differs by one from the state detected by the 4 "decoder trigger 12 „

The external start signal on the bus. Start trigger 12 is transferred to the unit state in which it is before the time fixed by decoder 5. Counters 2 and 3 of pulses and frequency divider 13 are opened, and element 6 opens. The first pulse received after start is the counter The 2 pulses are transferred to the state fixed by the decoder 4, and at the output of the element And 6 a first pulse is generated by the device-generated sequence. At the end of this pulse, a pulse appears at the output of the generator 7, in which IR 2 pulses through the key block 8 are written down in the adder 11 the code of the number p c. The pulse counter 3 continues to remain in the initial state, since no pulses have yet been received at the input of the multiplication unit 10. As the counter of the 2 pulses is inverse, then through p, the device operation cycle, it will again return to the state fixed by the decoder 4, and at the output of the element 6, the second pulse of the generated sequence will go. This process is repeated g times, and a series of g pulses is produced at the output of the device with constant pulse intervals.

After passing through the shaper of the 7th pulse, the frequency divider 13 is triggered and delivers a delay through the block 9 to the multiplier 10 one pulse, which at the output of the multiplier 10 is transformed into a stack of pulses received at the counting input of the counter 3 pulses and then to the adder eleven-. Due to this, each rth pulse of the generated sequence increases the number at the output of the adder 11 by a units and thereby forms the code of the interval value in the next series of pulses. This code is rewritten into the counter 2 pulses after the termination of the r-th

51497721.

Claims (1)

pulse, but before the appearance of the (g + 1) -th formula of the invention of the pulse at the input of the counter 2 pulses The pulse sequence generator according to ed. St. No. 1370737, about t. Next, the change of intervals occurs and that with, every g of pulses. The process of increasing the reliability of the genera- tion continues until the counter-ratora is inserted into it, the divider clock 3 pulses go into the current state connected between the forma- tion fixed by the decoder 5, after the field and the delay unit, the input is set by trigger 12 And the settings of the frequency divider are connected to the device and are ready for the next start-up, with the full output of the trigger.