SU1490719A1 - Device for conversion of signals - Google Patents

Abstract

This invention relates to a measurement technique. The purpose of the invention is to reduce distortions in the structure of the input data. The device contains a control unit (CU) 1, consisting of binary counters 2 and 6, a programmable counter 3, an el-4 command fixation and an OR-5 element, as well as a memory block (PS) 7. In BP 7 The input data is recorded by iterating through all the addresses of signals received from counter 6. After BP 7 is filled with input data, the signal from the output of the last digit of counter 6 overturns 4 command latchings and BP 7 switches to reading this data to the device output va. In this case, the output data is analyzed for the presence in BP 7 of an integer number of input data periods. The process of changing the output data is performed from the first to the sixth analysis step, and at the sixth analysis step, a complete coincidence of the whole number of input data periods with the BP 7 is achieved. This ensures the reduction of distortions in the input data structure. 3 il.

Description

lirjii: jii Tniiiip RELATES TO K and the measuring technique and can be used in the spectral and correlation analysis of signals.

The purpose of the invention is to reduce distortions in the structure of the input data.

Figure 1 shows the electrical block diagram of a signal converting device; FIG. 2 is a functional view of the input control signal of the duration of the time window; FIG. on fig.Z - spectrogram of the output signal.

The device contains a control unit 1, which consists of the first

binary counter 2, programmable counter 3, command fixation element 4, element 1-XI 5 and second binary counter 6, as well as memory block 7. In addition, in the diagram of FIG., Denotes a run 8, a synchronization input 9, a data output 10, and a time window duration control input 11.

The device works as follows.

From the Reset input, a signal is sent to binary counter 2, programmable counter 3, element A, and element OR 5, through which it is fed to the input of binary counter 6.

This signal sets binary counter 2, programmable counter 3, command fixation element 4 and binary counter 6 to their initial state, while the outputs of binary counter 2, programmable counter 3 and binary counter 6 are set to logical zeroes, and the output of command fixation element A is set to the state corresponding to the permission to write the input data to the memory unit 7. Input data can be supplied to memory block 7 from data input 8 in the form of analog values, if memory block 7 is, for example, a device with charge coupling or in the form of binary levels and a digital code, if the memory element is statistical operative storage device. After the signal is removed from the reset input, which has reset all the device circuits to the initial state, the data is written to memory block 7. Recording is performed by iterating through all the addresses A A, ..., A of the memory block, to which signals from the binary code are received from the output of binary counter 6. These

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the signals are the result of the conversion of a continuous series of sync pulses to the binary counter 6 from the synchronization input 9, which also passes to the programmable counter 3. The volume of the counters

6 and 3 are equal to the size of memory block 7 and are expressed in bits of binary information. After the memory data block 7 is filled with the input data, the signal from the output of the last bit of the binary counter 6 overturns the command fixation element 4, which is closed. In this case, the memory block 7 goes from the recording mode of the input data to the reading mode of this data and outputting it to the output 10.data. The output is analyzed, for example, using a spectrum analyzer.

(not shown), if in the block

7, because there is not an integer number of input data periods, then the program has the form shown in FIG. After the first step of the analysis, the second Diary is started, for which, from the synchronization input 11, a single pulse is fed to the binary counter 2, which changes its output at its output

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The control commands received at the input of the programmable counter 3. This leads to the fact that the volume of the programmable counter 3 in bits of the binary information becomes smaller. For example, if its total volume is 1024 bits in the first step, then on the second gate the volume is 1023 bits, and so on. The decrease in the volume of the programmable meter 3 leads to the fact that the reset signal from its output goes to the input of binary counter 6 until it is full. sync pulses, i.e. at the same time, the NL is issuing 10 data of one bit of input data to the output. In the second step, at output 10, the data will be two bits less, at the third step, three bits, and so on. until a result is obtained that indicates that an integer number of periods of input data were packed in the volume of memory block 7. Fig. 3 shows the spectrogram of the output data change from the first to the sixth step, and at the sixth step, an almost complete coincidence of an integer number of input data periods with the capacity of memory block 7 was achieved. After the output data has been measured, all the device circuits are reset and new data is recorded.

Claims (1)

Invention Formula A signal conversion device comprising a serially connected control unit and a memory unit, the input and output of which are the input and output of the device, characterized in that, in order to reduce distortions in the structure of the input data, the control unit is designed as an element of command fixation connected the first binary counter, programmable counter, the element OR, and the second binary counter, the inputs of the sign bits of which are connected: 5 A907196 to the address inputs of the memory block, the write-read signal input of which is connected to the output of the commit element. the counter and the first input of the first binary counter are inputs of the Reset signal, the third input of the programmable counter and the second input of the second binary counter are inputs of the synchronization signal, the second input of the first binary is of the counter is input to control signal duration time window. ten 15 FIG. 2 Fig.d