SU1481767A1 - Signature analyser with quasisynchronization - Google Patents

Abstract

The invention relates to devices for technical diagnostics and can be used to monitor and search for defects in electronic equipment. The aim of the invention is to expand the functionality of the device. The implementation of the invention allows to obtain stable signatures for objects in which the output sequence cannot be synchronized with the clock pulses received at the clock input of the signature analyzer from the clock pulse generator of the object of diagnosis. The analyzer contains a K-bit shift register 1 and an adder 2 modulo two, an indication unit 3, a counter 4 for N cycles, a generator of 5 clock pulses with a frequency that is not less than N times the clock frequency of the object to be diagnosed, the first element OR 6 , second element OR 7. REGISTER 1 SHIFT AND SUMMATOR 2 BY MODULE TWO WILL FORM A SIGNATURE FORMER. WORK OF THE ANNOUNCEMENTS RECORDING OF A SINGLE SIGNAL IS PRODUCED AT THE MOMENT OF ITS RECEIPT AT THE INPUT OF THE SIGNATURE ANALYZER WITH QUASI SIN-CHRONIZATION. 1 IL.

Description

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This invention relates to technical diagnostics and can be used in diagnosing digital electronic equipment.

The aim of the invention is to enhance the functionality by ensuring the control of sequences of short pulses with high duty cycle.

The drawing shows the functional diagram of the analyzer.

The analyzer contains a shift register 1 and an adder 2 modulo 2, an indicator 3, a 4 clock counter, a generator of 5 clock pulses, whose frequency is at least n times the clock frequency of the diagnostic object, the first element OR 6, the second element OR 7, a clock input of shift register 8, input 9 "Reset shift register, input 10" Start of the analyzer, input 11 "Stop of the clock generator and information input 12 of the analyzer. The register 1 shift and the adder 2 modulo two form the shaper 13 signatures.

The signature analyzer works as follows.

At the time of the start of diagnostics, input 10 "Start is fed to a logical unit. It is fed to the input 9 "Reset shift register 1, the second input of the second element OR 7 and the input" Start clock generator. Shift register 1 under the action of a logical unit received at its input “Reset 9” switches to the initial state, in which a zero signal is recorded in all its bits. Zero signals from the outputs of all bits of the shift register 1 are fed to the inputs of the display unit 3 and to the input of the adder 2 modulo two. In all bits of the display unit 3, zeros are highlighted.

A single signal received from the input 10 "Start to the second input of the second element OR 7, from the output of the second element OR 7 is fed to the input" Reset counter 4 by n cycles.

Counter 4 is reset. A single signal received from the input 10 “Starting to the start input of the generator 5 clock pulses and starts it, while the generator begins to generate clock pulses received at the first input of the counter 4.

If during the time required for the generator 5 clock pulses to generate n pulses, the information input 12 of the analyzer does not receive a single signal, the counter 4 per p clocks, counting the n clocks received at its first input from the generator output 5 clocks, goes back to the initial state by issuing a single signal at the first input of the first element OR 6. A single signal from the output of the first element OR b is supplied to the clock input 8 of the shift register 1. Since the input 12 of the analyzer at this moment

a zero signal arrives; in the first bit of shift register 1, a modulo sum is recorded for the contents of those t-1 bits whose outputs are connected to the inputs

adder 2 modulo two. The information of all bits of shift register 1 is shifted one bit to the right.

If, after arriving at the input of the counter 4 for the n cycles of V pulses (), to the input

- 12 the analyzer receives a single signal, it simultaneously arrives at the first input of the second element OR 7, the second input of the first element OR 6, the input of the adder 2 modulo two and the sum of the modulus is recorded in the first bit of the shift register i.

two contents of its m-1 bits, the outputs of which are connected to the input of the adder 2 modulo, and the unit entering the input of the adder 2 modulo two, which is the information input 12 of the analyzer.

The information of all bits of the c-bit shift register is shifted one bit to the right. The information of the bit is erased.

Then the process is repeated with the new

5 of the initial state of the bits of the k-bit register 1 shift.

At the moment of the end of the diagnosis, a single pulse is applied to the input 11 of the Stop Generator 5 clock pulses. 5 clock pulse generator stops

0 to generate a sequence of pulses arriving at the input of counter 4 by n cycles, counter 4 stops. Since, at the same time, signals from the checked object cease to arrive at the input 12 of the analyzer, the state of the register bit 1

5, the shift at this moment is recorded and the resulting signature is displayed on the display unit 3.

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Claims (1)

Invention Formula A quasi-synchronization signature analyzer containing a signature generator, a clock generator, a counter and a display unit, the information input of the signature generator is the information input of the analyzer, the output generator group of the signature generator characterized in that, in order to extend the functionality by providing control sequences of short pulses with large th duty ratio, the analyzer comprises two OR gates, the first inputs of which are combined and connected to the information the input of the analyzer is the second input and the output of the first element OR are connected respectively to the overflow output of the counter and the clock input of the signature generator, e1481767. eo the second input of the second element OR of the connector of the clock generator stop input with the reset input of the driver of signatures, pulses is the input of the Stop analysis and the input of the clock generator start, the output of the second element OR of the pulses is the input of the Start-up analysis with the reset input of the counter.