SU1480128A1 - Deserializer-serializer - Google Patents

Abstract

The invention relates to measuring computing. The purpose of the invention is to increase the speed of the converter. The converter contains a digital-to-analog converter (D / A converter) 1, a resistive voltage divider 2 with a division factor of 2 connected between the input bus and an output of the DAC 1, a resistive voltage divider 3 connected between the input bus and the common bus, the outputs of the dividers are connected respectively to the first and second inputs of the switch 4, the output of which is connected to the information input of the analog-digital converter (ADC) 5, the adder 9 and the control unit 10. The outputs of the ADC 5 are connected respectively to the information inputs of the adder 9, the output rows MSBs of which are connected to the inputs of the DAC 1 and the output of the control unit 10 are connected with the control inputs of the ADC and the adder switch. 1 il.

Description

The invention relates to electrical measuring and computing equipment and can be used to convert analog signals in a digital code, the instantaneous values of which occupy a wide dynamic range.

The purpose of the invention is to increase the speed of the device. 1Q

The drawing shows a structural diagram of the ADC.

The circuit includes a digital-to-analog converter (DAC) 1, resistive * voltage divider 2 with a dividing factor of 2 ”, 2 resistive voltage divider 3, switch 4, analog-to-digital converter (ADC) 5, made on a parallel converter 6 with additional - 20 solid comparators 7 and 8, adder 9, control unit 10.

The device operates as follows.

In the first cycle, along the edge of the signal 25 Clock 1, generated by the control unit 10, the signal C ₎ , / 2 ' ¹⁺ ' is fed to the ADC input 5 and converted by it into the high-order code η.

The level of the input signal 30 is set using a scaling amplifier (not shown) in accordance with the formula

U = 2 -m · ύ U, MOX 25 wherein U ^ _MC1KC ^_ upper level sensor input signal;

m is the scale factor;

AP is an ADC quantization step 5.

By slice signal clock 1 η MSBs code is entered in the adder 9, the output of the DAC 1 is set compensating voltage inverse polarity in accordance with formula 45 ^U u, AH- ^{P (1} '*) ⁴ⁿ CDP> gdedi ~ _DAC analog equivalent units Jr. DAC discharge, which is selected in this device in such a way that 4Ccc _DP = 2 · όυ.

In this case, the voltage of '55 is set at the second input of the switch 4

U = 2 ⁿ AU * F _g [and _x / 2 ^П41 · JU], where F-Γ · 1 is the symbol of the fractional part de.

litel.

This ensures coordination of the converted signal in the second cycle of the ADC, since U _X2 . έ 2 ^η · Α U.

In the second cycle, along the edge of the signal, Clock 2, the voltage U is supplied to the ADC input 5. It is converted into the low-order code η, and after the cut of this signal, the low-order code is entered into the adder 9.

Dynamic conversion errors are corrected using additional comparators 7 and 8.

So, if at the moment of the second conversion I Ц _ЦДП I? IU _x I, then the comparator 8 is activated and the unit of the least significant bit is subtracted in the adder 9. After setting a new value, the ADC 5 generates the code η of the least significant bits.

Otherwise, when Шс Дп 1 <<| U _X I, an additional comparator 7 is triggered and in the adder 9 the unit of the least significant digit is added _relative to the higher bits of the transformation.

Claims (1)

SUMMARY OF THE INVENTION A parallel-serial analog-to-digital converter containing a first resistive voltage divider, the first input of which is an input bus, the second input is connected to the output of the digital-to-analog converter, and the output is connected to the first information input of the switch, the output of which is connected to the information input of the analog-to-digital converter whose control input is connected to the first output of the control unit, and the outputs are connected to the corresponding information inputs of the adder, the first and second outputs are the first and second output buses, and the first output is connected to the input of the digital-analog converter, the second output of the control unit is connected to the control input of the adder, and the group of outputs is connected to the control inputs of the switch, characterized in that, for the purpose to improve performance, a second resistive voltage divider is introduced into it, the first input of which is an input bus, the second input is connected to a common bus, and the output is connected to the second information input of the switch.