SU1453437A1 - Imitator of radio signals - Google Patents

Abstract

The invention relates to radio engineering and communications. The purpose of the invention is to improve the accuracy of imitation. The simulator of radio signals contains the master G-r 1, the transducer 2 forms of pulse signals, as well as the driver 9 time intervals. The goal is achieved by introducing an AND 5 element, an OR 6 element, a register 7, and an accumulating adder 8 into the device. The converter 2 of the pulse waveform contains serially connected memory block 3 and DAC 4, and the BjSe interval imager 9 contains sequentially connected trigger , element OR NOT, counter, AND element, second trigger and switch. The simulator operation represents a sequence of cycles, on each of which a sequential reading from the memory block 3 of the codes of the values of discrete samples of the function of signals, the conversion of the sequence of read codes into a signal of a given form over a time interval equal to the duration of the signal shaper 9, and the formation of pause duration. 2 z o f-ly, 2 ill. with (L

Description

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The invention relates to radio engineering and communications and can be used in simulators for training radio operators and test benches for the functional control of radio equipment.

The purpose of the invention is to povigeniya imitation accuracy.

Fig. 1 shows a structural electrical circuit of a radio signal simulator; Fig. 2 is a structural electrical circuit of a time interval generator.

The radio signal simulator contains a master oscillator 1, a transducer of 2 pulse waveforms containing a block of 3 memory and a 1C1 phyro-analog converter 4, element AND 5, element OR 6, register 7, accumulating adder 8 and driver 9 bur. a small interval containing the first 10 and second 11 triggers, the element OR NOT, 12, the counter 13, the element AND 14, the switch 15 and the first 16 and second 17 registers.

The simulator of radio signals works as follows.

Before work, the signal parameters are loaded. For this, an initial setup input is used, which is an information bus connected to the informational inputs of information receivers — register 7 and first 16 and second 17 registers of driver I 9, accumulating adder 8, block; 3 converter 2, synchronization line, connected to the synchronization inputs of register 7, the first 16 and second 17 registers, and the second input of the element OR 6, and five control lines, each of which is connected to. control input of one of said receivers of information. The control lines make the entry of the initial state or the accumulation of the sum of the accumulating adder 8, the writing or reading of the block 3,

Parameters may be loaded in the following sequence.

1. Load the step code of changing the address equal to one to record the sequence of codes of the function of the form in register 7.

2. Load the zero starting address into the accumulating adder 8.

3. At the same time, the sequence of waveform value codes in block 3. In this case, the recording mode in block 3 is identified by the level that permits recording, on the corresponding control line, the recording is effected by the sync signals from the output of the EI 6 element, the sequence of write addresses is generated by the sync signals from the output of the element OR 6 by the accumulating adder 8 by successively summing the code of its state with the input from the output of the register 7 by the unit code. Upon completion of the loading of block 3 in the register of accumulating adder B, the zero code of the starting address is automatically set. ....

4. Download code pulse duration Tj in the first register 16 of the driver 9,

5. Load code duration pau between pulses T, in the second register 17. ...

6. Loading the code of the approximation step into the register 7. The initial loading of the device must contain all the steps. Further, if necessary, reconfigure the device to another

The simulated reload signals can contain either all of the steps, or some of them, for example, steps 1–3 to control the form with constant time parameters, or steps 4–6 to control the time parameters of the signals (duration of the following intervals) with a constant function of their form .

The simulator operation represents a sequence of cycles, on each of. which sequential reading is made from block 3 of the memory of codes of values of discrete samples of the function of signals, the conversion of a sequence of read codes into a signal of a given shape over a time interval equal to the duration of the signal generated by shaper 9, and the formation of a pause duration.

In the initial state, the first trigger 10 is set to zero, and at the output of element 1W-NOT 12 a zero level is formed, which, arriving at the control input of the counter 13, allows the clock pulse to write to the counter a return code of the video pulse duration, which

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It passes through the OR-NOT 12 element to the control input of the counter 13, and the next clock pulse into the counter 13 enters the pause duration code sent to its information input from the output register 17 through the compensator 15, to the control input of which a signal is output from the trigger 11 output Entering a new code into counter 13 causes the signal to end at. the output of the second element And 14, as a result of which the counter 13 can again function S in the direct counting mode. With the falling edge of the signal from the output of the AND element 14, the second trigger 11 changes its state (in this case to zero), and the formation of the duration of the simulated signal ends. After the end of the duration of the rectangular video pulse at the output of the imaging unit 9, the element 5 is closed at the first input, the codes are not read from the memory block 3, and the accumulating accumulator 8 is set to zero, which is preserved until the formation of the next video impulse 9. The shaping of the pause duration ends when the status code of the counter 13 reaches its maximum value, while the counter 13 is entered in the same way as the pulse duration code described, and the second trigger 11 is again set to one.

The end of the radio signal simulation occurs as a result of

3 memories repeat-40 ° D control signal simulator

the end of the simulation that sets the first trigger 10 to the zero state.

arrives at the information input of this counter from the output of the first register 16 through the switch 15, controlled by the signal from the forward output of the second trigger 11, held in the zero state by the signal from the reverse output of the trigger 10.

The function of the device starts from the moment the control signal of the start of the simulation arrives at the input i of the control. This signal sets the trigger 10 to one state, allowing the driver 9 to operate. The lulevo level from the output of trigger 10 is inverted by the OR-NO 12 element, allowing the counter 13 to operate in the counting mode. In addition, the start of generation pulse sets the single state of the second trigger 11, which is transmitted to the output of the imaging unit 9.

The unit level from the output of the imaging unit 9 opens the element I 5 at the first input, allowing the passage of pulses from the output of the master oscillator 1 to the element OR 6, from the output of which the data of the impulses arrive at the synchronization inputs of block 3 and accumulating adder 8. At the same time, from block 3, the control input of which is assumed to be a read enable signal, the form function codes read by addresses are read, forming 25

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with my accumulating adder 8, which, for each clock pulse, carries out the summation of the code of its current state with the code of the step of approximate simulation.

The process of sequential reading block codes

until the end of the duration of the first video pulse generated by the imaging unit 9. During this time, codes describing the shape of the radio pulse are read from memory block 3. The codes read from block 3 are fed sequentially to the input of a digital-to-analog converter 4, which performs continuous conversion of incoming

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Claims (3)

1. Radio signal simulator containing series-connected input codes in proportional to this ko-50 master oscillator and driver I will give the voltage of an electrical signal. As a result, a pulse of a given shape is formed at the output of the digital-to-analog converter 4. The state code of the counter 13, successively increasing, reaches its maximum value, so at the output of the second element I 14 a signal is generated, which Invention Formula 1. Radio signal simulator containing series-connected time intervals with a control input, as well as a pulse waveform transducer, characterized in that, with an increase circuit of an imitation accuracy, register and series-connected element AND, element OR and accumulating adder, the output of which is connected to the address input of the transducer 1453437 l pulse waveforms, the set input of which is combined with the second inputs of the adjusting adder, the OR element and the time interval former and with the input of the register whose output is connected to the third input of the accumulating adder, the first input of which is combined with the control input of the pulse transformer signals, and the output of the master oscillator is connected to the first input. is a clock input counter, 2. The simulator according to p. 1 of a tl and informational input of which is connected by a switch with the fact that the switch is transformed-T °, and the puller of the form of the pulsed holds successively coe "H ° Le ° JOB time intervals". .. v-unified, the control input of which is the combined setup inputs of the first and second flip-flops, and the output of the AND element is connected to the second 25 input of the OR-NOT element , pulse waveform converter. 3. The simulator according to A.1, about tl and - ches. By the fact that the time interval generator contains the first trigger connected in series, the element, the counter, the AND element, the second trigger and the switch, to the first and second inputs of which the outputs of the first and second registers are connected, the inputs of which are combined and are the installation input of the time generator. ... CJ1JJHU United a memory block and a digital-analog converter, and the address, installation and control inputs of the memory block are the same-name inputs pulse waveform converter. 3. The simulator according to A.1, about tl and - ches. By the fact that the time interval generator contains, in series, the first trigger, element, counter, element I, second trigger and switch, the first and second inputs of which are connected to the outputs of the first and second registers, the inputs of which are combined and are the installation input of the timers