SU1422173A1 - Digital frequency meter - Google Patents

Abstract

The invention can be used in C1 measurement and automatic control systems. The digital frequency meter contains the generator 1 reference frequency, triggers 2 and 3, counters 6-10, elements I-16, delay elements 17-19, distributor 21 pulses, group elements 22 and 24 and element 23. In the frequency meter triggers 4 are entered and 5, a delay element 20 and an indication unit 25. The proposed frequency meter has an increased reliability of operation due to the development of interrelated commands to control its nodes. By ordering the definition of the algebraic result of the integer and fractional parts of the period of the measured frequency, the accuracy of the measurement is improved. 3 il. S

Description

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with

The invention relates to measurement technology and automation and can be used in measurement systems and automatic control.

The purpose of the invention is to improve measurement accuracy and reliability of operation. FIG. 1 is a block diagram of a digital frequency meter; in fig. 2 and 3 are time diagrams that explain the operation of the digital frequency meter. ; The digital frequency counter is a reference frequency ipaTop 1, triggers 2-5, counters 6-10, And 11-16 elements, delay elements 17-20, 21 pulse distributor, And 22 group element, And 23 element, And group element 24 and a display unit 23.

The first generator output 1 of the reference frequency is connected to the first inputs of flip-flops 2 and 4, the output of flip-flop 2 is connected to the first input of the flip-flop 3, the second input of which is connected to the second input of the flip-flop 4, the first input of the trigger 5 is connected to the corresponding inputs of the counters 6, 8 and 9, the second output of the generator 1 is connected to the second and first inputs of the elements AND 1 1 and 12, respectively, the first input of the element 11 is connected to the output of the trigger 2, and the output to the second input of the counter 6, the first output of the trigger 3 is connected to the second input of the element And 12, the second output d - to the second and first inputs of the elements 13 and 14, respectively, the third output of the generator 1 is connected to the first input of the element 13, the outputs of the elements 13 and 14 are connected to the counting (first) and adjusting (second) inputs of the counter 7, group the output of which is connected to the second group input of the group element I 22, the first group input of which is connected to the first group output of the pulse distributor 21, the input of which is connected to the output of the element 12, the output of the distributor 21 is connected to the first input of the element 23, the second input of which first connected to the second input of the trigger 3 and the output of counter 6, the output of the element And 23 is connected to the counting inputs of counters 9 and 10, the group output of the counter 9 through the group element And 24 is connected to the installation group input of the counter 10, the output of which is connected to the second input of the trigger 5, the output of which is connected to the second input element And 15, the first

the last input to the second input of the trigger 4 and the input of the delay element 18, the first and second inputs of the element AND 1 6 are connected respectively to the output of the trigger 4 and the second input of the trigger 2, and the output to the second input of the counter 8, the third input of which is connected to the output of the element And 15, the output of the delay element 18 through the delay element 19 is connected to the second input of the group element AND 24, to the installation input of the counter 10 and to the input of the delay element 20, the output of which is connected to the installation input of the counter-box 8, the second input of the trigger 2 is connected to the input element 17 is the delay and is the input of the frequency meter, the group outputs of the counters 8 and IO and the output of the delay element 18 are connected to the corresponding inputs of the display unit 25.

Digital frequency meter works as follows.

When the measurement intervals are uninterrupted, the following expression is valid (Fig. 2a, b, c

to

de tol the i-th benchmark reference

measurement time interval;

n is the number of pulses of the measured frequency for il t, is the part of the period of the measured frequency at the beginning of the subsequent (i + l) -ro measurement interval;

  the period of the measured frequency, which coincided with the beginning of the subsequent measurement interval;

d t is the part of the period of the measured frequency at the beginning of the current measurement interval; THi - the period of the measured frequency coincided with the beginning of the current measurement interval.

Thus, the measurement of the frequency is included in the calculation of the number of the eld and fractional parts of the periods of cha.

Stokes f for the reference time interval T.

If the counting of pulses of the whole part (Fig. 3 a, b) is performed. from the second pulse of the measured frequency from the start of the measurement w, the time equal to one full period of the measured frequency can be allotted for auxiliary operations (calculating | Q fractional part, correcting the integer part counter from the fractional calculation results, recording information from the counters to the output devices).

FeHepatop 1 generates pulses J5 of the reference frequency Fg, f, f, and for the convenience of dividing ff Kf, where the coefficient K can take values that are multiples of the base of the numbering system of the measurement result, and is determined by the degree of accuracy with which it is necessary to calculate the fraction -. Noah parts. So, if it is necessary to have a measurement result in the ten-ary number system with an accuracy of ten - 25ths of a period, K 10,

With the appearance at the output of the generator 1 of the next pulse of the reference measurement interval T, the trigger .2 is set to a state in which the element I 11 opens. Counter 6 begins to receive pulses from hours. a hundred f | for measuring the interval l (Fig. 2d, d). The trigger 4 is set to a state in which the element AND 16 is closed, and the pulses of the measured frequency are not received in the counter 8 of the integer part.

With the arrival of the first (after the beginning

35

pulse measurement of the measured frequency trigger 2 is set to the state in which the element 11 is closed and the number At ends up, and trigger 10 is in the state in which elements 13 and 14 are closed, access to the counter 7 and 1 is 1 pulses of the quantization of the whole period with the frequency f, and the reset pulses P15 is reduced, and the element 12 opens, starting up the distributor 21 pulses. The process of dividing the contents of counter 6 (t) by the contents of counter 7 () begins.

In counter 7, by the time of dividing there is a NUMBER T of the last one before the beginning of the measurement of the period of the measured frequency, since, due to the presence of the delay element 17, the reset pulse to the input of the element 14 comes later.

73

than the prohibition signal from the output of trigger 3, and the counter 7 at the beginning of this nepiio does not reset.

j t. T Ki

carried out to

. Q

5 0 5

about

five

goals of units by a fractional cyclic subtraction of the number T ,: and A t- with the aid of an element 22, controlled by the distributor 21 with a frequency g.,. At the end of each cycle of subtracting the impulses from the output of the last cascade of the distributor 21 Through the open section of the element I, 23 is fed to the input of the addition, the counter 9, and to the input of the counter, 1.0. The division occurs until the moment when the senior digit bit of counter 6 is accumulated, i.e. until the remainder in the counter of the dividend is less than the divisor. Thus, at the output of counter 6, a signal is formed. End of division, which closes the element AND 23, prohibiting the passage of pulses to counters 9 and 10, sets trigger 3 to state 1. At the same time, elements 13 and 14 are opened (the periodic reset and counter 7), element E 12 is closed, and division ends.

In counter 9, the result of dividing the termination is recorded, and in counter 10, -ixt

tb-f. jut at, -f T,;, T ,, “T,. ,, tat dividing in the preceding cycle.

- result, if C -

on

Jsl

0

the output of the loan of the counter 10 is formed by the impulse of the loan, which sets the trigger 5 in the state where the element 15 is closed. At the end of the division, the correction of the result of the whole part is not carried out, i.e. no additional unit (Formula 1) is recorded, since it was occupied during the exercise.

l t g - whether;

, at the output of the account If 4-H.

0

The 1fi-i 10-chick loan pulse is not formed, and the trigger 5 remains in a state in which the AND 15 element is open, allowing the additional unit to be recorded at the End of division signal, according to the formula ().

In addition, the End of Division signal sets the trigger 4 to the state at which the element AND 16 opens, allowing the passage of pulses

of the frequency to the counter 8 of the integer part, starts the delay line from the delay elements 18-20.

The delay element 17 provides for the elimination of the reset of the counter 7 from the first pulse of the measured frequency fj in the measurement interval Tc, which simultaneously affects the trigger 2, and the last - on the trigger 3, closed Element I 14 to locate this pulse on the reset input of the counter 7. Minimum duration Delay Element .17 determined by time

The signal from the output of the delay element 20 sets the counters 6, 8 and 9 to the zero state, preparing them for the next measurement cycle, and the trigger 5 to the state in which the element 15 is open. The total time of all elements of the delay tjg 4 T. All

20

25

thirty

35

passing the signal from the moment of impact, the auxiliary operations end at input R of trigger 2 until the end of the crushing of element I 14 (by the signal from trigger output 3), and Maximum - with the safety factor of reliable operation taking into account the fluctuations of the time parameters of the indicated elements of the circuit in question.

Delay elements 18-20 are designed for the same purpose as element 17 for time diversity of auxiliary operations, namely: element 18 provides for a delay in the signal for recording information into display unit 25 from counters 9 and 10 for the time (with a safety factor) transient processes in the counter 10 from the last signal from the output of the element And 23, which in principle in time can coincide with the input signal of the element 18 (from the output of the counter 6); element 19 provides a delay in the census operation of information from counter 9 to counter 10 with respect to the previous operation (census from counter 10 to indication (ii) block 25; element 20 ensures a delay in resetting counter 9 from the previous information census operation.

The minimum durations of the delay elements 18-20 are determined by the time the signals travel through the respective chains and are selected similarly to the delay considered for the element 17.

The signal from the output of the element 18 writes the result (il) -ro of the measurement cycle from the counter 8 of the integer part and the counter 10 of the fractional part to the display unit 25, which is a buffer register that receives the information of the counters 8 and 10 and stores it until the end the next measurement cycle, and its associated digital

40

45

50

55

sec to the moment of occurrence of the second pulse of the measured frequency. Beginning with the second pulse of the measured frequency i-ro of the measurement cycle comes to the counter 8 of the integer part through the open (signal from the output of the trigger 4) element AND 16 before the start (i + O-ro of the measurement interval T (y (1 + 1).

With the appearance of the leading edge of the signal Fo (i + l) -ro of the measurement cycle, these processes are repeated. The result of the i-ro measurement cycle is obtained

(Jt; ./

after the end of the division at

.

this in the counter 10 fractional part for / 4t,; & t: f.j

the number of tr is written - /

 CHS-ti and

Starting from the second pulse, from the moment To (i + l) starts, counter 8 counts the integer part of the (i + l) -ro measurement cycle, etc. These operations are repeated.

By generating interconnected commands to control the nodes of a digital frequency meter, the reliability of its operation is increased. Due to the ordering of the definition of the algebraic result of the integer and fractional parts of the period of the measured frequency, the measurement accuracy increases.

Claims (1)

Invention Formula Digital frequency meter containing a reference frequency generator, the first output of which is connected to the first input of the first trigger, the output of which is connected to the first input of the second trigger and to the first input of the first element And, the second input of which is connected to the second output of the reference frequency generator and to the first input of the second element And, the second input of which is connected to the first output of the second trigger, and the output is connected to the input information from counter 9. scoreboard to display this information. The signal from the output of element 19 opens the group element I 24 and overwrites the input S of the counter 10 / St. T: The signal from the output of the delay element 20 sets the counters 6, 8 and 9 to the zero state, preparing them for the next measurement cycle, and the trigger 5 to the state in which the element 15 is open. The total time of all elements of the delay tjg 4 T. All auxiliary operations end- auxiliary operations end- sec to the moment of occurrence of the second pulse of the measured frequency. Beginning with the second pulse of the measured frequency i-ro of the measurement cycle comes to the counter 8 of the integer part through the open (signal from the output of the trigger 4) element AND 16 before the start (i + O-ro of the measurement interval T (y (1 + 1). With the appearance of the leading edge of the signal Fo (i + l) -ro of the measurement cycle, these processes are repeated. The result of the i-ro measurement cycle is obtained (Jt; ./ after the end of the division at . this in the counter 10 fractional part for / 4t,; & t: f.j the number of tr is written - /  CHS-ti and Starting from the second pulse, from the moment To (i + l) starts, counter 8 counts the integer part of the (i + l) -ro measurement cycle, etc. These operations are repeated. By generating interconnected commands to control the nodes of a digital frequency meter, the reliability of its operation is increased. Due to the ordering of the definition of the algebraic result of the integer and fractional parts of the period of the measured frequency, the measurement accuracy increases. Invention Formula Digital frequency meter containing a reference frequency generator, the first output of which is connected to the first input of the first trigger, the output of which is connected to the first input of the second trigger and to the first input of the first element And, the second input of which is connected to the second output of the reference frequency generator and to the first input of the second element And, the second input of which is connected to the first output of the second trigger, and the output is connected to the input pulse distributor, the bit outputs of which are connected to the first inputs of the third group element and whose outputs are connected to the corresponding bit inputs of the first counter, the second counting input of which is connected to the output of the first element And, the second inputs of the third group element And are connected to the output of the second counter , the third output of the reference frequency generator is connected to the first input of the fourth element I, the second input of which is connected to the second output of the second trigger and the first input of the fifth element I, and the output d is connected to the counting input of the second counter, the setup input of which is connected to the output of the fifth element, the second input of which through the first delay element is connected to the second input of the first trigger. and is the frequency meter input, the output of the second delay element is connected to the installation input of the third counter , the counting input of the fourth counter is connected to the output of the sixth element And, and the group output through the seventh group element And is connected to the group discharge input of the fifth counter, the counting input of which is connected to you the sixth element And, the first input of which is connected to the output of the first counter and the second input of the second trigger, and the second to the output of the pulse distributor, characterized in that, in order to increase measurement accuracy and reliability of operation, a fourth element is introduced into it delays, eighth and ninth elements And, third and fourth triggers and a display unit, the first input of the third trigger is connected to the first output of the Reference Frequency Generator, the second input - to the output of the first counter, to the input of the third delay element and to the first input ohm of the eighth element h And, the output of the third trigger is connected to the first input of the ninth element And, the second input of which is connected to the frequency counter input, the output of the ninth element And connected to the counting input of the third counter, the third input of which is connected to the output of the eighth element And, the second input which is connected to the output of the fourth trigger, the first input of which is connected to the installation input of the first counter, the second input of the fourth trigger is connected to the output of the fifth counter, the output of the second delay element is connected to the installation in The first and fourth counters, the fourth delay element input is connected to the third delay element output, and the second input is connected to the second delay element and the second input of the seventh And group element, the second delay element input is connected to the third input of the fifth counter, the third outputs, The fifth counters and the output of the third delay element are connected to the first, second and third inputs of the display unit. t H) ъ s V4 Isj V. one WITH;; l -d with : .to 4i S: