SU1383511A1 - Device for checking sensitivity of radio receivers via parastic reception channels - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to increase the reliability of the control. Device contains signal generator 1, amplitude comparator 2, driver (F) 3 start pulse, RS-flip-flop 4.1, 4.2, control block 5, reference signal F 6, indicator 7, matches 8.1, 8.2, decoder 9, And 11.1 elements 11.2, counter 16, divider 17, recorder 19 band-pass filter 21, rectifier 22, controlled radio receiver 27. In order to increase the reliability of the control, a third RS flip-flop 4.3, three elements OR 10.1, 10.2, 10.3, memory block 12, block were entered 13 differentiations, 14 single pulses, keys 15.1, 15.2, multiplier 18, delay element 20, two memorize block 23, 24, frequency 25, block 26 extremum signal. 1 3.p. f-ly, 2 ill. (L

Description

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The invention relates to radio engineering and can be used to automatically measure and control the susceptibility levels of radio reception by side channels, and also to automatically measure and record the deviation of receptivity levels of radio receivers by side channels from the given standard and frequencies; The purpose of the invention is to increase the credibility of the control. FIG. Figure 1 shows the structural electrical circuit of the proposed device; in fig. 2 is an embodiment of a memory block. I A device for monitoring the susceptibility of radio receivers through the receive side channels contains a generator 1 (signals, amplitude comparator 2, (|| actuator 3 trigger pulses, 1: First, second and RS triggers .1, 4.2 and 4.3, control unit 5, driver 6 the reference signal, the indicator 7, consisting of the first with a white board 7.1 Malfunction, the second light board 7.2 Norm and the third light board 7.3 Not the norm, the first 8.1 and in the second 8.2 element of the same match, the decoder 9, the first in , the second and the third elements OR lb.1, 10.2 and 10.3, the first and second elements And 11.1 and 11.2 , memory unit 12, differentiation unit 13, single pulse generator 14, first AND | second keys 15.1 and 15.2, counter 16, divider 17, multiplier 18, recorder 19, delay element 20, polar filter 21, expander 22, П | ЕРВЫЙ and the second storage units 2 | 3 and 24, the frequency meter 25, block 26, the output of the signal extremum, shows a controlled radio receiver 27.

The memory unit 12 contains (FIG. 2) the address counter 28, 4t of operational storage units 29.1-29.4t, 4p operational memory, their units 30.1-30.4p.

The device works as follows.

At the initial moment of time, the third RS-flip-flop 4.3 is in the initial state, at its direct output a logic voltage O chi is generated, which sets the memory block 12 to the Record mode (Fig. 1).

from 5 0 5 0 5 0

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 The frequency f of the signal generator 1 is set to the upper limit of the control range f. The input of the monitored radio receiver 27 provides a signal of levels x equal to a given norm x, which generates a signal y at the output of the amplitude detector and monitors the radio receiver 27, comparing further with the level of the reference signal y, which is produced by the shaper 6 of the reference signal. Control unit 5 performs a smooth change in the frequency of the signal generator 1 in a controlled frequency range of fft f - f.

As a result of the monitoring, in the event of a malfunction of the controlled radio receiver 27 at the output of the amplitude comparator 2, the difference signal D yu-Wo is negative () in the controlled frequency range f - f and the driver 3 of the start pulse is locked. With his release on the first RS-flip-flop 4.1 will not receive any impulse. The first and second RS-triggers 4.1 and 4.2 are in the initial state 1. In this case, the four outputs of the decoder 9 are in the following states: U, f О, U2 and 11 0. At the end of the control range at the frequency f from the output The limit switch for tuning the signal generator 1 to the second inputs of the first 8.1 and second 8.2 coincidence elements and the first element 11.1 receives the voltage U, the first element 8.1 of the coincidence operates, including an indicator 7, on the first light panel 7.1 of which the Fault message lights up, the second and the third light boards 7.2 and 7.3 do not include are. In this case, the first and second inputs of the first element 11.1 generate voltages of logical 1, which form a voltage of logical 1 at its output, and the frequency tuning of the signal generator 1 by the servo drive of control unit 5 is stopped.

In the case that the receptivity of the side reception channels is satisfied with the established rate, when the frequency of the generator 1 of these lines coincides with the frequency of the main channel of the controlled radio receiver 27, the output signal of the amplitude comparator 2 produces a positive signal, O, which is fed to the driver 3

a trigger pulse, generates one pulse of a pointed shape, transferring the first and second RS-flip-flops 4.1 and A.2 from state 1, 1 to state O, 1. At the same time, at the outputs of the decoder 9 and, V O, a. At the end of the control range at frequency f from the output of the ring switch, the tuning of the generator of 1 signals to the second inputs of the first 8.1 and second. Of the 8.2 coincidence elements and the first element 11.1, the voltage Uy arrives, the second coincidence element 8.2 operates, including the indicator 7, on the second light panel 7.2 of which the signal Norma is lit. The first and third light boards 7.1 and 7.3 do not turn on, as U, Uj O, the frequency tuning of the generator 1 of the signals by the servo drive of the control unit 5 is terminated in the same way as described.

In case of dissatisfaction of the receptivity of the side channels of reception at the established rate at the frequency of the main reception channel of the monitored radio receiver 27 and at the frequency of at least one side reception channel (or at the frequencies of two side reception channels), the level of susceptibility of the monitored radio receiver 27 that does not satisfy the established rate at the output of the amplitude comparator 2, a signal is formed twice, and at the output of the generator 3 of the start pulse, two pulses are generated, which translate the first and second RS-triggers s and 4.2 4.J

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state 1, O, as a result of which the outputs of the decoder 9 have a voltage of 11, 1 V O, and U, 0, the voltage U, enters the indicator 7, on the third light panel 7.3 of which the signal is illuminated Not normal frequency tuning of the signal generator 1 continues. In this case, if the frequency of the signal generator 1 coincides with the lower limit of the passband of the main reception channel of the monitored radio receiver 27, the voltage Vi is applied at the output of the bandpass filter 21, which flows through straight line 22 to the first input of the second element 11.2, to the second the input of which from the output of the amplitude comparator 2 receives the voltage of a lu. With

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On the output of the second And 11.2 element, a voltage of logical 1 is formed, which opens the second key 15.2. The voltage & y from the output of the amplitude comparator 2 also opens the first key 15.1.

The counter 16 calculates the number n of periods of oscillations of the intermediate frequency signal from the intermediate frequency output of the controlled radio 27 during the tuning time of the generator of 1 signals in the passband of the main receiving channel of the controlled radio 27 at the level Hm. This information from the output of the counter 16 is fed to the input of the channel channel of the memory unit 12 and through the open second key 15.2 to the input of the first storage unit 23. The counter 16 and the first storage unit 23 are in the information recording mode. When the frequency of the signal generator 1 coincides with the resonant frequency of the main reception channel of the monitored radio receiver 27, a pulse is generated at the output of block 26, which starts the frequency meter 25 to measure the frequency of the main reception channel of the monitored radio receiver 27. This information from the output of the frequency meter 25 is fed to the first input of memory block 12 and is remembered in it.

When the frequency of the signal generator 1 coincides with the upper limit of the passband of the main reception channel of the monitored radio receiver 27 at the level x, j at the output of the amplitude comparator 2, the voltage Lu becomes equal to logical O, the first and second keys 15.1 and 15.2 blink, and the back front voltage The output of the amplitude comparator 2 is differentiated by block 13, the pulse Ug from the output of differentiation block 13 returns the counter 16 to the initial state, and through the second element OR 10.2 switches the memory block 12 to the next line for istratsii information about the frequency and bandwidth of the next channel 27 receiving radio controlled.

When the frequency of the signal generator 1 coincides with the lower bandwidth of the side channel of reception of the monitored radio receiver 27, the output of the amplitude comparator {a 2 also produces a signal.

513

which opens only the first key 1: 5.1. The counter 16 calculates the number n; the oscillation periods of the iijana intermediate frequency frequency from the output of the monitored radio receiver 27 during the tuning time h; the frequency of the generator 1 of signals in the passband of the side channel of the monitored radio receiver 27 at the level Hz. This information is stored on the corresponding line of memory block 12 (Fig. 2). When the frequency of the oscillator 1 of the signals 1 coincides with the resonant frequency of the side reception channel of the monitored radio bath 27, block 26 is triggered. It starts the frequency meter 25 and the information on the frequency of the side reception channel 21 is remembered on the corresponding line: e of memory 12. After passing through the frequency of the oscillator 1 of the bandwidth signals of the side channel, the first key 15.1 is closed, the counter 16 returns to the original state, and the memory block 12 is transferred to the next line and so on.

At the end of the control range at the frequency f from the terminal off-tuning of the signal generator 1, the voltage Ug is applied to the second trigger of the first element 11.1 and the S-input RS-flip-flop 4.3. The voltage of the logic 1 from the output of the first element And "11.1" is fed to the input of the control unit 5, and the frequency tuning of the Signal Generator 1 is stopped. The first RS flip-flop 4.3 transmits the S state of the logical 1, and its direct and inverse outputs ifia are the second and the third inputs of the Memory 12 are received respectively (1p, the logic 1 and the logic. In memory 12, the address counter is reset 28, transferring the operational storage units 29.1-29.4t and 30. 1-30.4p. Of both memory channels to the read mode. Thus, the memory unit 12 is transferred to the readout mode of the information stored therein, starting with the first line. the output of block 12 of the memory voltage logical O and logical V through the third element OR 10.3 start the generator of 14 SIDYUCH pulses.The pulse formed by them is fed to the second input of the first storage unit 23 and

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puts it into the readout mode of information about the bandwidth of the main reception channel of the monitored radio receiver 27, which from the output of the first memory of block 23 arrives at the first input of the divider 17. The pulse from the output of the generator 14 is single ;. pulse is also fed to the input element 20 of the delay. From the outputs of the delay element 20, the control pulse is sequentially fed to the control inputs of the divider 17, multiplier 18, recorder 19, and through the second element OR 10.2 to the fourth input of memory block 12 to take information from the next line. In this case, in the divider 17, the result of dividing n; / Pa is generated, and the multiplier 18 calculates the absolute excess of the susceptibility level of the monitored radio receiver 27 via a side channel of reception of a given norm by the formula. p / rd For this, the second input of the multiplier 18 from the output of the second storage unit 24 in the digital code receives information about the signal level of the 1 x generator. The registrar 19 captures the deviation of the level of susceptibility of the monitored radio receiver 27 for each side reception channel from the predetermined norm and the frequency of this channel.

The magnitude of the delays between pulses from the outputs of the delay element 20 is selected based on the time required to perform the actions in the divider 17 and the multiplier 18, as well as to record the results in the recorder 19.

When moving to the next line of memory block 12, if there is information about the bandwidth of the side reception channel, the generator of 14 single pulses is triggered and the described actions are repeated, and so on until all the lines of memory block 12 are scanned in which information is contained. Thereafter, the processing and recording of information is terminated.

Claims (2)

1. A device for monitoring the susceptibility of radio PRNs on po113 side channel reception channels containing a decoder, a shaper of a reference signal, a serially connected control unit and a signal generator, whose information output is the input of a monitored radio receiver, the first And element, sequentially connected amplitude comparator, the first input of which is monitored the radio receiver, and the second input is connected to the output of the reference signal conditioner, the trigger pulse driver, the first RS trigger and the second RS trigger, the first and second outputs Which are connected to the first and second inputs of the decoder, the third and fourth inputs of which are connected to the second and third outputs of the first RS flip-flop, the indicator, the first and second match elements, the first inputs of which are connected respectively to the first and second outputs of the decoder, and the outputs of the first and The second match elements are connected respectively to the first and second inputs of the indicator, the third input of which is connected to the third output of the decoder, the second inputs of the first and second match elements are connected to the output end A signal generator switch, a counter, a divider, a recorder, a series-connected band-pass filter whose input is connected to an information output of a signal generator, a rectifier and a second element I, the second input of which is connected to the output of an amplitude comparator, in order to increase the reliability control, entered the first element OR, the first, second, third and fourth inputs and output of which are connected respectively to the first, second, third and fourth outputs of the decoder and the first input of the element This AND, the second input and output of which are connected respectively to the output of the limit switch of the signal generator and the input of the control unit, the first key, the first and second inputs and the output of which are connected respectively to the intermediate frequency output of the monitored radio receiver, and the output of the amplitude comparator and the first the counter input, the memory block, the signal extremum extraction block connected in series. d 0 5 "P 5 0 five 18 the input of which is connected to the first input of the amplitude comparator, and the frequency meter, the second input and output of which are connected respectively to the information output of the signal generator and the first input of the memory unit, the third RS flip-flop, the input and the first and second outputs of which are connected respectively to the output of the limit switch of the generator signals and the second and third inputs of the memory unit, a serially connected differentiation unit, the input of which is connected to the output of the amplitude comparator, and a second OR element, the output of which is Connected to the fourth input of the memory unit, a multiplier connected in series to the third element OR, whose input is connected to the first output of the memory unit, a single pulse generator and a delay element, the first, second, third and fourth outputs of which are connected respectively to the first input divider, with the first input of the multiplier, with the first input of the recorder and the second input of the second element OR, the first input of which is connected to the second input of the counter, serially connected second key, the first input of which is connected to the output the second element And, and the first storage unit, the second input and output of which are connected respectively to the output of the single pulse generator and the second input of the divider, the third input of which is connected to the first output of the memory unit, the second output of which is connected to the second input of the recorder, the third input which is connected to the output of the multiplier, the second input of which is connected to the output of the divider, the second storage unit, the output of which is connected to the third input of the multiplier, the output of the counter is connected to the 5th input of the memory unit and the second a second key entry. .one 2. A device according to claim 1, characterized in that the memory block contains an address counter, a counting input and an input whose reset are the fourth and third inputs of the memory block, respectively, and two memory channels, the first of which contains 4 tons of operational storage blocks , where m is the number of frequency measurement bits, and the second one contains, GP8  m of the short-term storage blocks, where n is the number of channel strip measurement bits, while the bit inputs of the operational memory blocks of the first and second memory channels are connected to the bit output of the address counter, the combined inputs of the line selection of all operative memory blocks of the The keys to the counting input of the address bookkeeper, the combined inputs. Recording all the operational memory of the blocks is the second input.  ten memory block, information memory memory inputs of the memory channel are the first input of the memory unit, the first output of which are the combined memory output memory outputs of the first memory channel, information inputs of the memory storage memory output blocks of the second memory channel The fifth input of the memory block whose second output is the combined outputs of the operational memory blocks of the second memory channel.