SU1358094A1 - A-d converter - Google Patents

Abstract

The invention relates to a pulse technique and can be used to build high-speed and precision amplitude analysis paths in multichannel spectrometers. A device containing an analog storage device 1, a main DAC 6 and a DAC 7 leveling, a sequential approximation register 4, a clock generator 3, a source 5 of the reference voltage, two auxiliary registers 10 and 11, a binary leveling counter 9, an adder 12, a comparator , 8 and the control device 2, in order to increase speed, additional parameters were introduced. the new DAC 18, t / 2 D-flip-flops 19-20, the third auxiliary register 16, the second adder 15. 1 Cp f-ly, 2 ill., 1 tab. I (L cond al as:

Description

11358094

The invention relates to a pulse technique and can be used, for example, to build high-speed and precision amplitude analysis paths in multichannel spectrometers.

The purpose of the invention is to increase the speed and accuracy of the conversion.

Figure 1 shows the block diagram of the IQ converter; 2 is a block diagram of a comparator.

An analog-to-digital converter (ADC) contains an analog locker set in a single state and a unit is added to the content of the binary leveling counter 9. The high potential of the senior discharge output of the RPP 4 includes

 ""about -

First-class discharge current with a weight of 2 DAL 6, and high potentials of D-flip-flops include, respectively, pedestal steel discharge currents with weights of 2–2 DACs 18, and an initial pedestal is formed equal to 2 + ..., + 2 single quanta . The output of the DAC 7 razravnivaniya sets the current times20

device (AMS) 1, block 2 control of equilibrium (Ip). At the end of the name, the clock generator 3, the register 4 of the successive approximation (.RPP), which is built on the basis of the K155IR17 type IC with inversion of the discharge outputs using the logic circuits NOT, SOURCE 5 of the reference voltage Discharge first main DAC 6, ha - bit second leveling DAC 7, comparator 8, leveling binary counter 9, first 10 and second 11 auxiliary registers, first adder 12, resistor 13 converting the output voltage of the ASU 1 into its output current (first out-) 5 current level 5

the pulse at the fourth output of the control unit 2, the ABC is transferred to its storage mode via its control input, simultaneously starts from the generator 3, which controls the operation of the PS1 4, and the first inputs of the control unit 2 are reflected.

Comparator 8 analyzes the algebraic sum of the currents from the ACC 1, the main DAC 6, the DAC 7 leveling and the third DAC 18. The output current (igbix) of the ARC 1 is proportional to the amplitude of the voltage being measured. The results of the comparison of clocks are set at 14 of the main DAC 6, the second sum is recorded in RPF 4, which is in its torus 15, the third auxiliary register 16, and the current output 17 of the third

t dtt 1 about -,. 1. J

the queue controls the output currents of the main D / A converter 6. The usual analog-to-digital conversion is performed using the bit-wise conversion triggers, output 21 of the conversion of conversion 2 uses, from the first 19 to the 20th, the design of the DFD 4.

The comparator 8 is implemented on the operational amplifier 22, the third resistor 23 of the comparator 24, the voltage, the first resistor 25, the first capacitor 26, the fourth resistor 27, the first and second diodes 28 and 29, the second capacitor 30 and the second resistor. torus 31.

The Converter operates as follows.

The measured voltage is fed to the information input of the CCD I. With the arrival of the input logic signal

c to increase the output current of the D / A converter 6 by the maximum leveling current.

Algebraic output amount

40 current (l out) АЗУ 1 and leveling current (lpa, 3) is measured by the algebraic sum of the currents of the main (IOCH. And additional dson.) D / A converter 6 and 18 DAC, and the additional current

45 is formed by pedestal currents and duplicate currents.

The remaining bits of the DAC 18 are used to increase the speed of the main DAC 6, and the bits with

Starting on the first input of unit 2 controls - 60 weighing 2, 2.,, .., 2 D / A converters 18

,,,

At its fourth output, a negative impulse appears (with a duration of 500 n), which sets the initial state of the S-input (RP4 4 (i.e. its major Qt, + p4l is the bit output and the conversion end SS) in one state, and all other bit outputs - in zero), D-flip-flops are set in one state and one is added to the contents of binary leveling counter 9. The high potential of the high-level discharge output of the VFR 4 includes

 ""about -

First-class discharge current with a weight of 2 DAL 6, and high potentials of D-flip-flops include, respectively, pedestal steel discharge currents with weights of 2–2 DACs 18, and an initial pedestal is formed equal to 2 + ..., + 2 single quanta . At the output of the DAC 7 razravnivaniya sets the current times

equal (Ip). At the end of the

pulse on the fourth output of the control unit 2, the ABC is transferred to its storage mode by its control input, the generator 3 starts up simultaneously, which controls the operation of the PS1 4, and the first inputs of the control unit 2 are reflected.

Comparator 8 analyzes the algebraic sum of the currents from the ACU 1, the main DAC 6, the DAC 7 leveling and the third DAC 18. The output current (igbix) of the ARD 1 is proportional to the amplitude of the measured voltage. Comparison results for clocks to increase the output current of the DAC 6 by the maximum leveling current.

Algebraic output amount

40 current (l out) АЗУ 1 and leveling current (lpa, 3) is measured by the algebraic sum of the currents of the main (IOCH. And additional dson.) D / A converter 6 and 18 DAC, and the additional current

45 is formed by pedestal currents and duplicate currents.

The remaining bits of the DAC 18 are used to increase the speed of the main DAC 6, and the bits with

60 weighing 2, 2.,, .., 2 DAC 18

,,,

used to set the pedestals, which in the process of conversion are sequentially turned off in order of decreasing of their weights, with this 55, in the same order, duplicate bits 2 are compared

t-1

, m-1 -3

.. ,, 2 D / A converters with an algebraic sum of the currents presently present at the input of the comparator 8.

, ..., 2 DAC 18

Bits 2

are taken into account when forming the ending-. target output code of the ADC,

In the first cycle of the PSC 4, the conversion begins by subtracting the current of the older one (j bit of the DAC 6 from the resulting current, which is currently the sum + Ipaj minus the additional current (V formed by the DAC 18 by first turning on the discharge currents having weights , ..., 2 °, i.e. all pedestal steel currents.If the high discharge current (2) of the DAC 6 is less than the resulting current, then a low potential is formed at the output of the comparator 8, and the high discharge current of the DAC 6 remains 13

.

with enabled. If the current is higher than 20 +5), it requires that the accuracy of the comparison) of the DAC 6 is greater than the result was much better (2 ° + ... + main), then the potential at the output of the comparator is +2, quanta. This easily reaches 8 is changed, and the high-order current of the D / A converter 6 is turned off, and the trail, since the lower bits require less settling time than

Best Senior Output

25

(Q.

) RPF 4 is reset to zero-level bits, where large currents are switched.

The subsequent every three cycles of conversion are similar to the preceding three cycles, only measurements occur when the bit is turned on, which is the highest in the previous comparison, in the penultimate one; Those RPP 4 on the leading edge are transferred the youngest D-flip-flop 19 to And its next () output is set to 35 zero state, which turns off

in the DAC 18, the last pedestal having a weight of 2, and the comparison of the backup bit of the DAC 18 is repeated at zero pedestal. Setting this current (and the resultant current 40 bit and bit 2 of the DAC 6 in the latter can be muted by the included first cycle of the BFD 4 requires that the comparison accuracy is much better than a single quantum.

This sequence of measurements makes it possible to establish the highest order of the DAC 6 and DAC 18 rows with the required accuracy until all pedestals are removed.

At this time, the weighing of the output current - the CAM 1 ends. AT

 h + pn

 new state. Comparison of currents in the first conversion cycle is carried out roughly within the established pedestal, i.e. up to 2 + + + ... + 2 quanta (channel), and in the next conversion cycles it will be adjusted to the desired accuracy. At the beginning of the second cycle RPP

It is cast in a single state, ko-. This includes the next largest current, having a weight of 2 DACs 6. As a result of a comparison with the resultant bits of a DAC 6 according to the results of previous comparisons, this current remains turned on or off as in the previous clock cycle.

The subsequent bits, ".., 2 D / A 6, are processed in the same way, starting with the third cycle, and end with (n-m) -th clock-register 4. In the next clock (n-m + 1) DFR 4 in the same way duplicate bit (2) of DAC 18 is processed, and then bit 2 of DAC 6 is processed in the same way in tact (n-m + +2). In cycles of DFG 4 from the first to (n-m + 2) inclusive, comparison: It is accurate to 2 + + + ... + 2 ° channel (quantum).

50 ka (Ig,)

 FPA 4, at the end of the conversion, a code is established that is equivalent to the sum 1c, +. The transformation ends with the appearance of a negative differential at the output of the CC PFR 4, which is fed to the second input of the control unit 2 and which is at its fifth output.

1358094 /

At the beginning of the stroke (n-m + 3), RPF 4 sets a high potential at

its output (.), on the leading edge of which the upper D-flip-flop 20 is reset to the zero state, which turns off the discharge current with a weight of 2 D / A converters 18, and compares the backup current to the resulting current

0 weighing 2 DACs 18, i.e. the second time there is a comparison with a current having the same weight () only at different pedestal values: the first comparison in the measure (n-m + 2) also in the pedestal-5 steps (2 ° +. ..), and the second in the measure (p-ha + 3) with a pedestal (2 + + ... +). Install bit

DAC 18 and later bits 2

m-l

and D / A 6-cycles (n-m + 4) and (n-m +

+5) - requires that the comparison accuracy was much better (2 ° + ... + + 2), quanta. It easily reaches

c, since the lower bits require less settling time than

older bits where high currents are switched.

At this time, the weighing of the output current - the CAM 1 ends. AT

50 ka (Ig,)

 FPA 4, at the end of the conversion, a code is established that is equivalent to the sum 1c, +. The transformation ends with 55 by the appearance at the output of the SS РПП 4 of the negative differential, which is fed to the second input of the control unit 2 and which is on its fifth output 51358094

a strobe pulse is generated. 18,

open rio lee

According to this pulse, the codes are rewritten into the first 10, second 11 and third 16 auxiliary registers, respectively. In addition, the AMC 1 enters the sampling mode by its control input, a pulse appears ready and the first inputs of block 2 are unlocked.

In the adder 15, the control codes of the D / A converter 6 and the D / A converter 18, which come from the outputs 2, are summed up. . ., 2 first register 10 and outputs 2, ...

at

2 of the third register 16, and at the output ig, the conversion time of the ADC is

adder 15 generates code 2,. ".,

2

The code in the adder 15 and the code of the lower bit of register 10,

in tact (n + p + l),,.

The table shows that the older six bits manage to set 20. (turn them on when rough comparison) with the required accuracy to remove pedestals 2 ° and 2, and the dead bits are set for a time less than 3.0i -

having a weight of 2, goes to the first inputs of the first adder 12, to the second outputs of which from the Inverse outputs of the second register 11 the leveling code is inserted. In the adder 12

the codes are subtracted, enrolled- 25 The proposed solution allowed

their inputs (i.e., the leveling code is subtracted from the total converted code). The result is the voltage corresponding to the 1st measured voltage, the signal is ready. The code is ready from the output of the adder 12 is copied to the external memory. After that, the converter is ready for the next conversion.

The transient process of setting the output current of the D / A converter 6 (.) Is exponential, and the time for establishing the most significant discharge current with an accuracy of half of the dead

bit is T

ast.

 91 where

L is a constant exponent (for example, for IC K1108PAG G 300/9 -33 NS, 300 not).

For an accurate 12-bit DAC, the accuracy ratios of setting the discharge currents in accordance with the table should be observed.

Graph and table of the dynamic error from the normalized time. / t are given in the literature and were confirmed with sufficient accuracy by experimental verification at the proposed ADC.

From the table conversion algorithm and the outcome of the correct determination of the two low bits of the ADC (at this moment all the pedestals are turned off are first determined by bit 2 of the DAC,

and then the low-order bit 2 of the D / A converter 6}, from which it follows that the minimum period of the generator 3 must be more than 2.

However, when determining the higher bit 2 of the DAC 6, all the pedestals (2 + 2 + 2 ° at) are included, which makes it possible to determine it not with an accuracy of 0.0125%, but with an accuracy of 8% and spend time according to the table, not 9t and ZG-

Thus, the period of the generator 3 must be at least 3t, and the total

at

ig ADC conversion time is

in tact (n + p + l),,.

The table shows that the older six bits have time to set 20. (when they are turned on for rough comparison) with the required accuracy to remove pedestals of 2 ° and 2, and the dead bits are set in a time less than 3.0i -

five

, increase: the ADC speed is doubled.

The speed of the comparator is determined by the voltage of its over-excitation, corresponding to the required conversion accuracy, which in turn is determined by half of the current of the low-power discharge used by the main DAC. (in this case, the D / A converter. With an increase in the accuracy of the conversion, the comparator over-excitation voltage decreases, and consequently, its speed decreases. With input signal ranges

Q 0-5 V and 4096 quantization levels, the half-half-bit size is ± 0.75 mV, and the half-half-current of the DAC 6 is less than 1 µA. These conditions determine the selection of a compass by input parameters.

The proposed solution eliminates the dependence of the speed of the comparator 8 on a given conversion accuracy, since the amplifier 22 operates in the proportional conversion mode at 25 resultant currents into the input voltage of the comparator 24 at times of equal current of the AMS 1 and DAC 6, 18, and 7. At this point, the response time of the comparator 24 is determined by the rate of rise of the output signal of the amplifier 22.

0

five

In the case of violation of the equality of the currents, the amplifier 22 due to the presence of a non-linear feedback circuit (diodes

28 and 29 - the resistor 27) will operate in a nonlinear mode, limiting the voltage at the input of the comparator 24. At the time of comparison with this accuracy, the output currents of the AMS 1 and DAC 6, 18 and 7, the over-excitation voltage is set to the direct input of the comparator 24 corresponding to its maximum speed.

The capacitor 30 and the resistor 31 form a positive feedback circuit of the comparator 24 necessary to eliminate its self-excitation.

Capacitor 26 provides amplifier stability, smoothing its transient response, narrowing the passband and suppressing excessive resonant noise.

Neither the current output 14 of the D / A converter 6 continuously maintains the potential of the virtual earth, the output resistance of the D / A converter 6 (m, e. The input resistance of the amplifier 22) is several ohms, which reduces the time constant of the input circuit of the amplifier 22. to a value less than 0 2 no.

The amplifier 22 should be broadband with a speed of increase of the output signal of at least 50 V / µs (for example, K574UD1, 154UD4 or hybrid micron KG02-UIZ, etc.),

Thus, the link: amplifier 22 — voltage comparator 24 increases the speed and accuracy of the conversion.

When using the KG02-OIZ amplifier, device KG 597SA2 and DAC K 1108 PA1 used in the pre-installed device: device 1.8 MKS conversion time, 1% differential nonlinearity in the dynamic range 200, while the thermal stability of the conversion coefficient is 0.025 % / 10 С, and zero characteristics - 0.3 channels / 10 С,

formula of invention

1, An analog-to-digital converter containing an analog storage device, a n-bit first diffraction converter and

-discharge second digital-to-analog converter, (n + p + 1) -discharge register of sequential approximation

40

ten

15

20

where p t / 2, reference voltage source, clock generator, two registers, binary pulse counter, first adder, comparator and control unit, the first input of which is the control bus, the first output — the bus is ready, and the second output is connected with a control input of an analog storage device whose information input is an input bus and an output connected to the first output of a current limiting element made on a resistor, the second output of which is combined by the outputs of the first and second digital-analogue connected to the input of the comparator, the inputs of the reference voltage of the first and second digital-to-analog converters are combined. The D-input of which is connected to the output of the comparator, and the S-input is combined with the counting input of a binary pulse counter and connected to the fourth output of the control unit, the input to the Secondly, it is connected to the output of the conversion of the serial approximation register, the E-input of which is a zero potential bus, the information inputs of the first and n-th bits of the first digital-analog converter and the first register are respectively combined and connected respectively to the first and (n + p + 1) -th sequential approximation register bit; the building inputs of the first and second registers are combined and connected to

p the output of the control unit

25

3035

0

five

The formation inputs of the second digital-to-analog converter and the second register are respectively combined and connected to the corresponding outputs. D binary pulse counter, the output of the first bit of the first register is connected to the input of the first bit of the railing of the inputs of the first adder, the outputs of which are corresponding, their output buses, and the second inputs are connected to the inverse outputs of the corresponding bits of the second register that differ by the fact that, in order to increase speed, a third (t + 1) -digit digital-analogue converter, t / 2 D-flip-flops, where mjn is 1, the third register, the second (p-1) -discharge adder, are entered into it the first inputs of which are connected to the corresponding The output outputs of bits, except for the first, first register, and the second inputs are connected to the corresponding outputs of the third register, the gate input of which is connected to the fifth output of the control unit, and the inputs of the bits of the third register, except the high, are combined with the inputs of the corresponding even bits , except for the third digital-analog converter, which has become synchronized, with the synchronization inputs of the corresponding D-flip-flops and connected to every third information output, starting from the second, the sequential approximation register, the inputs Settings c.1 of the D-flip-flops are combined and connected to the fourth output of the control unit, the outputs of the D-flip-flops are connected respectively to the inputs of odd bits, except for the older, third digital-to-analog converter, information inputs from toro

the first digital-to-analog converter and the first register, respectively, are combined and connected with the corresponding information ones, starting from the third to (m + p + l) -rb except every third, the outputs of the serial register, approximations the higher bits of a third of its digital-to-analog converter and the third the register are combined and connected to (t + p + 1) -th information output of the sequential approximation register register, information inputs from (t + 1) -x to (nl) -e first digital-to-analogue converter and the first register, respectively o are combined and connected to the corresponding informational outputs from the (t + p + 2) th (n + p) th output registers of the sequential approximation, the output of the second adder

Bit number yes

Crrj IIIi Z ll lIl JLT ---- I

1.5 2

3.3 4.

8094

yen

ten

IQ with the corresponding bits starting from the second, first inputs of the first adder, the information inputs of all D-flip-flops are connected to the common bus, the reference voltage of the third digital-to-analog converter is connected to the output of the reference voltage source, and the output of the third digital-to-analog converter is connected to the outputs first and second digital-to-analog converters. 2, the Converter according to claim 1, about t

with that

The goal is to increase the speed and accuracy of the conversion, the comparator is higher, more efficient on the operational amplifier, voltage comparator, two limiting diodes, four tokado-yads; their elements made on resistors and two accumulating elements made on capacitors, the non-inverting input of the operational amplifier is connected to bus zero

potential, and the inverting input is combined with the first output of the first capacitor, the first output of the first resistor, the inputs + and - respectively the first and second diodes

and is a comparator input, the output of which is the direct output of a voltage comparator, the inverse output of which is connected to the first output of the second capacitor, the second output of which is combined with the first output of the second resistor and connected to the inverse input of the voltage comparator connected to the first pin of the third resistor, the second pin of which is combined with the second pins of the first capacitor and resistor, the first pin of Q

45

The house of the fourth resistor is connected to the output of the operational amplifier, the second terminal of the fourth resistor is combined with the terminals - and +, respectively, of the first and second diodes, and the second terminal of the second resistor is a zero potential bus.

12

6.5

8 8,5

Editor L.Gratillo

Compiled K). Spiridonov

Tehred M. Didyk Proofreader S. Cherni

Order 6008/56. Circulation 900 Subscription VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushskay nab., 4/5

Production and printing company, Uzhgorod, Proprekna str., 4

Figg

Claims (2)

•Claim 1. An analog-to-digital converter containing an analog storage device, an η-bit first digital-to-analog converter and a ha-bit second digital-to-analog converter, (n + p + 1) -digit register of the sequential approximate 'I will give a binary pulse counter, □ and the output of the first bit a first register coupled to the input of the first bit of first inputs of the first adder, you .hody which are corresponding conductive output lines _55, and second rows are connected WMOs _e R inverted outputs of the respective bits of the second registers of a, characterized in that, in order to increase the speed of action, a third (w + 1) -digit digital-analog converter, w / 2 D-flip-flops, where w $ n - 1, the third register, the second (η-l) are introduced into it -digit adder, the first inputs of which are connected to the corresponding outputs of the bits, except for the first, first register, and the second inputs are connected to the corresponding outputs -jg of the third register, the gate input of which is connected to the fifth output of the control unit, and the inputs of the bits of the third register , besides the elder, combined with the inputs of the corresponding 15 even'discharges, In addition to the third digital-to-analog converter, which has become, with the synchronization inputs of the corresponding D-triggers, they are connected. for every third informational output ₂ , starting from the second sequential approximation register, the inputs of the setting in ”1 D-flip-flops are combined and connected to the fourth output of the control unit, the outputs of the D-flip-flops 25 are connected respectively to the inputs of the odd digits, except for the older one, third digital-to-analog converter, information inputs from the second to the m-th first digital-to-analog; the converter and the first register, respectively, are combined and connected to the corresponding information, starting from the third to the (t + p + 1) -th, except for every third, outputs of the serial register. approximations, the upper bits of the third digital-to-analog converter and the third register are combined and connected to (t + p + 1) -th information output of the sequential approximation register, information inputs from (w + 1) -x to (p-1) -th of the first digital-to-analog converter and the first register, respectively, are combined and connected to the corresponding existing from the (w + p + 2) -th (n + p) -th information outputs of the sequential approximation register, the outputs of the second adder are connected with the corresponding bits, starting from the second, first exits of the first adder, the information inputs of all D-flip-flops connected to a common bus, the input of the reference voltage of the third digital-to-analog converter is connected to the output of the reference voltage source, and the output of the third digital-to-analog converter is connected to the outputs of the first and second digital-to-analog converters. 2, The converter according to claim 1, characterized in that, in order to improve the speed and accuracy of the conversion, the comparator is made on an operational amplifier, a voltage comparator, two limit diodes, four current-carrying elements made on resistors, and two accumulating elements made on capacitors, the non-inverting input of the operational amplifier is connected to the zero potential bus, and the inverting input is combined with the first output of the first capacitor, the first output of the first resistor, inputs + ”and, respectively Actually, the first and second diodes are the input of the comparator, the output of which is the direct output of the voltage comparator, whose inverse output is connected to the first output of the second capacitor, the second output of which is combined with the first output of the second resistor and connected to the inverse input of the voltage comparator, direct input which is connected to the first output. third re- '. a resistor, the second terminal of which is connected with the second terminals of the first capacitor and resistor, the first terminal of the fourth resistor and connected to the output of the operational amplifier, the second terminal of the fourth resistor is combined with the terminals of the first and second diodes, respectively, and the second terminal of the second resistor is a bus of zero potential. Discharge Number ^ 1 j 2 ^ j 3 ~ J ~ 45 £ 6 Installation accuracy,% 25.4 12.8 6.4 3.2 1.6 0.8 0.4 0.2 0.1 0.05 0.025 0.125 1.5 2 3 3.3 4 5 6 6.5 7 8 8.59 Figg Editor L. Gratillo Compiled by Yu. Spiridonov Tehred M.Dvdyk Corrector S. Cherni Order 6008/56 Circulation 900 ¹ Subscribed VNIIIPI of the USSR State Committee for Inventions and Discoveries 113035, Moscow, Zh-35, Raushskaya nab., 4/5 Production and printing company, Uzhhorod, Prrektnaya str., 4