SU1357964A1 - Device for checking execution of programs - Google Patents

Abstract

The invention relates to computing and can be used to monitor the progress of a computer in a charge. The aim of the invention is to increase the reliability of the control. The device contains groups of registers, 11, groups of blocks of elements AND 2, 12, blocks of elements OR 3.14, decoders 4, 5, groups of elements И 7, 20, second group of elements ШШ 8, groups of elements 9, 13 delays, groups of blocks of elements ШШ 10, block 15 comparisons, elements OR 16-18, elements 19,23 of delay, element ШШ- НЕ 21 .. The device implements a hardware-software method of controlling the course of programs based on checking the admissibility of change of controlled variables. Violation of the conditions for the admissibility of changes to monitored variables indicates that an error has occurred in the program. And its implementation will lead to incorrect results. In this case, an error signal must be generated, which must be sent to the interrupt system. .1 il. i (Л С со 01 со а

Description

1135

The invention relates to a computational technique and can be used to control the course calculated in a computer.

The aim of the invention is to increase the Reliability of the control.

A device for controlling the execution of programs implements a hardware-software method of controlling the course of programs based on checking the permissibility of a change of controlled variables. Allocated controlled variables, each time when their current value changes, are checked for the correctness of one of the following conditions:

I. Pi Rd6. R p

2.r p-7. r Rd

3.R: p p (1)

BUT..

5. p Rd. 10 р р, where р is the current value of the controlled variable;

p is a valid value of the controlled variable; p - the previous value of the controlled variable.

Conditions (1) allow you to check the correctness of the program's progress by comparing the current value of the monitored variable with a valid or with a previous value.

Violation of the conditions for the admissibility of changes in the controlled variables indicates that an error has occurred in the prog program, and its execution will accordingly lead to. incorrect results. In this case, an error signal must be detected, which must be sent to the interruption system.

The drawing shows a functional diagram of the proposed device.

The device for monitoring the execution of programs contains the first group of registers 1, the first group of blocks of elements AND 2, the first block of elements OR 3, the second 4 and the first 5 decoders, the first group of elements OR

6, the first group of elements AND 7, the second group of elements OR 8, the first group of elements 9 delay, a group of blocks of elements OR 10, the second group of registers 11, the second group of blocks of elements AND 12, the second group of elements 13 delay, the second block of elements OR 14 , block 15 comparison, second 16, third 17 and first 18 ele5

0

Cops OR, the first delay element 19, the second group of elements AND 20, the element SH-KE 21, the element And 22 and

the second element 23 of the delay.

The device works as follows.

Each time the program is executed, codes of the type of controlled variables that correspond to the number of expression in (1) are programmatically entered into the first group of registers 1 from the first group of information inputs, and the second group of registers

5 11 from the second group of information inputs of the device through the group of blocks of elements OR 10 via the control signal received through the recording entry of the device and the group of elements,

0 OR 8 to the control inputs of the second group of registers 11, the permissible values of the monitored variables are programmatically recorded. When checking the correctness of the change of controlled variables into the corresponding registers 11 of the second group, the initial values of the variables are recorded. In the process of program execution, the first information group of device inputs receives a signal j corresponding to the current value of the controlled variable.

In this case, the second information group of inputs of the device enters

5, the signal corresponding to the number of the variable to be monitored, and to the second control input, the interrogation signal, which corresponds to the signal generated in the computer upon a change in ω (.

0 of the register in which the values of the controlled variable are recorded. The code corresponding to the value of the i-th number of the variable being monitored (, K) goes to

5 group of inputs of the decoder 5 with the third group of inputs of the device. In this case, at the i-M output, a signal appears that enters the i-th group of elements And 2 of the first block and the i-th

0 group of elements AND 12 of the second block, allowing the signal to pass from the i-x registers of the first 1 and second 11 groups to the input groups of the first 3 and second 14 blocks of the elements OR, respectively.

The signal corresponding to the verification code of the i-th controlled variable from the output group of the first block of elements OR 3 goes to the input group of depragafrator 4. At this output, where 1 is the verification code (1. 1.10), decoder 4 appears . Each output of the decoder corresponds to one of the possible options for checking the monitored variables. Each even output of the decoder 4 corresponds to the condition of checking the correctness of the monitored variables, and each pair of outputs corresponds to the same logical operation checking the monitored variables.

If the test code of monitored variables is 2, 4, 6, 8, 10, then from the corresponding output of the decoder 4 a signal through the element OR 18 and the first delay element 19 is fed to the first inputs of elements AND of the first group 7. To the second input i- ro element And 7 of the first group through the i-th element 9 of the delay of the first group from the i-ro output of the decoder 5 signal. At the same time, at the output of the i-ro element And 7 of the first group, a signal appears which, through the element of the same name OR 8 of the group, arrives at the control input of the corresponding register 11 of the second group, allowing recording of the signal corresponding to the current value of the i-th controlled variable, which on the information group of inputs of the i-ro register through the same name group of elements OR 10 blocks from the fourth information group of device inputs.

From the decoder 4, the signal corresponding to the check type code is sent to one of the inputs of the first group of elements OR 6, at the JM output, where j is the number of the checking condition (, 5), a signal appears that goes to the second input of the corresponding element AND 20 second group.

From the block of elements OR 14 the signal is conformable depending on the code of the type of verification or permissible,. ; or the previous value of the monitored variable is fed to the first group of inputs of the comparison unit 15 to the second group of inputs of which, via the second group of delay elements 13, necessary for verification synchronization, a signal corresponding to the current value of the monitored variable is received from the group of device inputs. As a result of comparison

A signal is generated at one of the three outputs of the comparison unit 15. In this case, at the first output of the signal generator, if the current value of the controlled variable is more than the allowable (previous) value, on the second, if the signals are equal, and on the third, if the current value of the variable is less than the allowable one. Since the first and second outputs of comparison unit 15 are connected to the inputs of the OR 16 element, and the third and second outputs of the comparison unit are connected to the inputs of the OR 17 element, the outputs of the OR 16 and 17 elements of the signal appear if the current value of the controlled variable not less than the acceptable (previous) value or not more.

Thus, the first inputs of each element And 20 of the second group receive signals corresponding to the 1 st) test conditions. If the verification conditions specified by the verification type code are not met, no signal is generated at any of the outputs of the element group AND 20, and an error signal is generated at the output of the OR-NO 21 element, which arrives at the first input of the element 22, at the second the input of which through the second delay element 23 (necessary to synchronize the arrival of the signal from the second control input of the device) receives the interrogation signal, and at the output of the element 22 there appears an error signal, which through the control output of the device enters the interrupt system.

The proposed device provides verification of the values or correctness of changes in the values of K of monitored variables, which means that

It can be used to control the correctness of the program.

Claims (1)

Invention Formula A device for monitoring the execution of programs containing the first group of registers, the first group of AND blocks, the first block of OR elements, the first and second decoders, the first and second elements OR, and the outputs of the registers of the first group are connected to the first inputs of blocks of elements AND of the first group, the outputs of which are connected to the corresponding inputs of the first block of elements SH, each output of the first decoder is connected to the second inputs of the corresponding blocks of elements AND of the first group, characterized in that, in order to increase the reliability of the control, the second group of registers, the second group of I blocks, the second block of the first output of the first decoder of sockets OR, the block group elements of OR, the first and second groups of elements are AND, the comparison block, the first and second groups of delay elements, the SHSHONE element, the first and second groups of OR elements, the AND element, the third OR element, and two delay elements, with the groups of information inputs of registers first the groups are the group of inputs for setting the device verification code, the group of outputs of the first block of elements OR is connected to the group of inputs of the second decoder, each pair of outputs of which is connected to the first and second inputs of the corresponding element OR of the first group, Each even output of the second decoder is connected to the corresponding input of the first SHS element, the output of which through the first delay element is connected to the first inputs of the AND elements of the first group, each output of the first decoder through the corresponding delay element of the first group is connected to the second input of the corresponding AND element of the first group, output of each element AND of the first group is connected to the first input of the corresponding element OR of the second group, the recording input of the device is connected to the second inputs of the NL elements of the second group, Exit each OR gate of the second group is connected to the input of recording of the corresponding register of the second group, a group of inputs specifying acceptable values of controlled variables of device connected to the first inputs of the respective block elements Hilti group, the output of each block element or connected group .s VNIIPI Order 6000/50 Circulation 671 Random polygons pr-tie, Uzhgorod, st. Project, 4 the information input of the corresponding register; tra of the second group, the output of each register of the second group is connected to the first input of the corresponding block of elements AND of the second group, the outputs of the blocks of elements AND of the second group are connected to the corresponding inputs of the second block of elements OR, inen with the second input of the corresponding block of elements AND the second group, the group of inputs for setting the number of the controlled variable of the device Not with the input group of the first decryption module, the input group for setting the current value of the monitored variable of the device is connected to the second inputs of the corresponding blocks of the group 21 and through the second group of delay elements with the input group of the first comparative number of the OR block, connected to the group the inputs of the second compared number of the comparison block, the higher, equal and less elevations, are connected respectively to the first input of the second OR element, to the second input of the second OR element, and to the first input of the third OR element, the output of each OR element of the first group is connected to the first input of the corresponding element of the second element of the second group, the output of the second element IL, the outputs More, Equal, and Less than the comparison unit and the output of the third element OR are connected to the second inputs of the first, second, third, fourth and fifth, respectively The elements AND of the second group, the outputs of which are connected to the corresponding inputs of the OR-NOT element, the output Equivalently the comparison unit is connected to the second input of the third IZH element, the output of the OR-NOT element is connected to the first input of the AND element, the polling input of the device through the second delay element is connected to the second vl: ohm element And, the output of which is the output of the device control result Subscription