SU1356268A1 - Message-transmitting system - Google Patents

Abstract

The invention relates to communication technology and can be used in remote control and information acquisition systems. The purpose of the invention is to increase the system capacity by reducing the re-reception time. The system consists of n network stations connected in a ring (CC), each of which has its own interface 3. Its operation is based on the fact that all the functions for managing and collecting messages can be. assigned to one of the SS, for example, SS 1. The system uses a cyclic ring with the transfer of authority (token) and the organization of two frequency-independent channels - information (IC) and control (CC). Information is collected from CC 2 by IC, and their control by CM. The system transmits four types of information: an information packet, a token, a control packet, and a receipt packet. The token, the control packet and the receipt packet from the CC 1 are transmitted by the Criminal Code, and the information packet and the receipt packet from the CC 2 by the IC. CC I sets one of two modes of operation: sequential polling of all CC 2 or polling of a given group of CC 2. The CC 1, 2 operation in these modes is explained. 8 il. SLR SP O) u a: oo

Description

The invention relates to communication technology and can be used in remote control and information acquisition systems for a selective substation from a main station.

The purpose of the invention is to increase the throughput of the system JY by reducing the re-reception time.

FIG. 1 is a block diagram of the message transmission system; in fig. 2 structural diagram (n-1) -th network station; in fig. 3 is a block diagram of the first network station; in fig. 4 - time diagram of the system; in fig. 5 is an example of the inclusion of micropro, instructor in the composition of network stations; in fig. 6 structure of packets transmitted in the system; in fig. 7 - the algorithm of the first network station; Fig 8 - the algorithm of operation (n-1) of network stations.

The messaging system of FIG. 1 includes the first network station 1, (n-) network stations 2, and n interface units 3.

In the block diagram of the (p-1) -network station of FIG. 2 denotes a first switch 4, a splitter 5, an amplifier 6, a filter 7, a receiver 8, a reception register 9, a data buffer 10, a transfer register 11, a switch 12, a first transmitter 13, an adder 14, a second switch 15s, a second transmitter 16, permanent memory block (PZB) 17, operative; storage unit (OZB) 18, block 19 reception-transmission, microprocessor 20 element AND 21, element OR 22, clock generator 235 synchronizer 24 reception, counter 25 address, indicator ™ tor 26 state receive, decoder 27 end of reception, the buffer 28. address address decoder 29, the transfer synchronizer 30, block 31 interrupt and trigger 32 modes.

The first network station (FIG. 3) contains the first key 33, the first filter 34, the first receiver 35, reception register 36, data buffer 37, transfer register 38, transmitter 39, adder 40, second key 41, OZB 42j OZB 43, block 44 transmission / reception, microprocessor 45, element E 46, ISh1 element 47, clock generator 48, reception synchronizer 49, address counter 50, first receive state indicator 51, end decoder 52

reception, address buffer 53, address decoder 54, transfer synchronizer 55, interrupt block 56, second filter 57, second receiver 58, and second receive status indicator 59.

Nodes and blocks of the messaging system can be implemented as follows.

0 The first and second keys 4 and 15, 33 and 4 are elements that provide a transit bypass of network station 2 when the power to the station is turned off (for example, a relay with

5 by the relevant contact group). Splitter 5 and amplifier 6 respectively provide separation and. ; enhance information flow dl. ensuring the work of a given acceptable distance between them.

The first filters 7 and 34 are tuned to the frequency of the control channel, and receivers 8, 33 and 58 contain a demodulator and the receiver itself. Buffers 28, 53 and 10, 37 of the address and data are bus drivers and can be executed on 589AP16 chips with three output states.

0

The first transmitters 13 and 39 operate with the modulation frequency of the control channel, and the second transmitter 16 operates with the modulation frequency of the information channel.

2 channels. Adders 14 and 40 can be implemented according to the scheme of summing operational amplifier.

OZB 18 and 43 and ПЗБ 17 and 42 are implemented on the basis of standard microcircuits.

0 constant and operational static memory. Transmission reception unit 19 is implemented on a 580BB51 microcircuit (serial interface). In this case, the address bus (one bit) of the device is connected with the contact 12 of the chip, the first, second and third control inputs of block 19 are contacts 13, II and 10 chips, a device information bus co-.

Q dinene with inputs-outputs DO-D7 of the microcircuit, and the input and output of block 19 are, respectively, the second input and output of the station and realize the serial interface Joint-2 (C2)

g GOST 18145-81. The corresponding pins 19, 24 and 22, 3, 17 of the known microcircuit are used. Interface unit 3 is a set of linear amplifiers (e.g., 170 series),

included in the corresponding input and code chains. The microprocessors 20 and 45 are implemented on the specialized chip 880D used in the prototype (one of the variants of the microprocessor Z 80). An example of switching on blocks 20 and 45 as part of stations 1 and 2 (the implementation of functional links) is shown in FIG. five.

The algorithms of operation of microprocessors 20 and 45 when turned on as part of the first network station 1 and (n-1) -th network station 2 are shown in FIG. 7 and 8 respectively.

The operation of the message transmission system is based on the fact that, in the application of local networks, in most cases, large volumes of information are not required to be transferred between different stations, and all control and message collection functions can be assigned to one of them.

The system uses cyclic

ring with the transfer of authority (marking of 25 microprocessor 20 through

ra) and the organization of two frequency-independent channels in one physical medium (cable, waveguide) - information channel (IC) and control channel (CC); The system provides for the collection of information from network stations 2 via IR and their management by CMs.

The system transmits four types of messages (Fig. 6): an information packet, a token, a control packet, and a receipt packet. The structure of the information and control packets is identical; it differs only in the type of information contained in it.

interrupt unit 31 and enables operation of the reception synchronizer 24, which forms the formation of shift gates for the reception register 9 using the synchronous frequency signals 30 from the clock generator 23. After the information byte is formed (counting 8 clock pulses), the receive synchronizer 24 outputs the corresponding signal to the second control microprocessor input 20; a two-way transfer to the high-impedance state of its information and address buses. When this state is reached, the microprocessor

The marker, the control packet and the packet 40 20 issue a confirmation signal for requisition from the first network station 1 are transmitted by the Criminal Code, and the information packet and the packet receipt from the network station 2 are transmitted via IR.

Start of operation is initiated by turning on the power. In this case, only the first network station 1, which, depending on the required environment, has the right to transfer the medium

sets one of the two possible modes gg or counter 25 of the address of the control | system operation 1.

In the first mode, all network stations 2 are sequentially polled; in the second mode, only the specified group of network stations 2 (or one | Station). The setting of the operation mode of the network station 2 is ensured by the transmission to it of the corresponding control packet received by the CM.

signal through the element OR 22. OZB 18 while in recording mode in the absence of a read signal from the fourth control output of the microprocessor 55 of the processor 20, and the address decoder 29 does not work, because its address inputs are connected only to the address outputs of the microprocessor 20, located at a given time in

56268

Consider the operation of the system in the first mode. The first network station 1 transmits a marker (FIG. 6) with the first of the network stations 2 connected to it in the direction of transmission (FIG. 4). Network station when receiving a marker (ftaK and receiving a control packet) works as follows

THAT (Fig. 2 and 8).

Through the first key 4, the marker sequence enters a splitter 5, which serves to match and separate the streams. Next marker

15, the sequence is fed respectively to amplifier 6, which provides compensation for the attenuation of the signal in the keys and splitter 5, through the adder 14 and the second key 15 to the input, and

20 through the filter 7 to the input of the receiver 8. When the first bit of the marker sequence is received, it is set to 1 receive status indicator 26. This signal forms interruption bins 31 and enables operation of reception synchronizer 24, which forms the formation of shift gates for reception register 9 using synchronous frequency signals 0 from clock generator 23. After the information byte has been formed (counting 8 clock pulses), reception synchronizer 24 outputs a corresponding signal to the second control input of the microprocessor 20; a two-way transfer to the high-impedance state of its information and address buses. When this state is reached, the microprocessor

water its address and information tires in a high impedance state. This signal resets (on the falling edge) the reception synchronizer 24 and unlocks the outputs of buffers 10 and 28 of data and addresses. In this case, the received byte of information is recorded from the information bus into the corresponding memory cell of the OZB 18 at the address of

no counter 25 address governing

signal through the element OR 22. OZB 18 while in recording mode in the absence of a read signal from the fourth control output of the microprocessor 20, and the address decoder 29 does not work, because its address inputs are connected only to the address outputs of the microprocessor 20 this point in time in

keyed (high-impedance state).

On the falling edge of the signal from the output of the synchronizer 24 of reception, the address of the counter 25 of the address is received, at which the next byte is accumulated, accumulated by the synchronizer 24 of reception.

The packet is received before those waves of the OZB 18 block are transmitted

. then, the gate end decoder 27 on the strobe signal from the second control output of the microprocessor 20 (at the moment of recording the byte of information carried out in each reception cycle) does not fix the coincidence of the received byte with some constant specified as the end of the packet, and this constant is equal for all kinds of bags

At the end of the packet reception (fixation of the byte End of the packet), the decoder 27 is triggered, resetting the indicator 26, which, in turn, blocks the operation of the reception synchronizer 24 and resets the interrupt signal of the microprocessor 20. However, since the fourth and fifth control inputs of the microprocessor 20 are different by priority interrupt inputs, then, upon receipt of this signal, microprocessor 20, in accordance with a fixed interruption vector, proceeds to the analysis packet of the received packet (Fig. 8). At the same time, the microprocessor 20 interacts with the PZB 17, ensuring the reading of the corresponding control commands through the And 21 element (the control of the PZB 17). The address decoder 29 operates synchronously in accordance with the address and control signals from the microprocessor 20.

If the received packet is Marker and it is intended for this network station 2 (the recipient’s address matches the station’s own address) and is received correctly (as determined by the test sequence), then if there is information to transmit, the network station 2 performs this information. .

Network station 2 in the mode of issuing information works as follows

If the analysis of the recipient's received address marker field has shown that it is intended for this network station 2, then if there is information to transmit, the microprocessor 20 performs

This is a transfer to the issue mode. The recording of the transmitted information block in the ACK 18 from the subscriber connected to this network station 2 is carried out through the corresponding interface block 3 in accordance with the established standard C2 or IRPS (truncated C2). For this in the absence of sai

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With the information block, the microprocessor 20 installs the transmission-reception unit 19 in the reception mode, writing into it the corresponding control word. Block 19 operates in a synchronous mode in accordance with the frequency received from the clock of the generator 23 o When establishing the synchronous mode and the signal about the presence of information at the subscriber, the block of information is overwritten in the CSP 18. If there is no signal about the subscriber having information to transmit and the buffer part of the PSA 18 is not filled, then this network station 2 forms a marker transmitted by the next network station 2 in the direction of transmission.

In the case of the presence of a block of information in the buffer of the BSS 18, it is issued in accordance with the packet format (Fig. 6).

For this, the microprocessor 20 sets the switch 12 to the position corresponding to the operation of the first 13 or second 16 transmitter.

The need for two transmitters operating at different frequencies is determined by the choice of control and information channels. If network station 2 transmits a token, the first transmitter 13 operating on the AC frequency is used, and if an information packet or receipt of a control packet is received, then the second transmitter 16 operating on the IR frequency is used. Simultaneously with the installation of the switch 12, the second output of the trigger 32 of the mode blocks the indicator 26 and interrupts the microprocessor 20. By this signal, the micro-. The processor 20 selects the sequence of bytes from the corresponding packet from FIG. 6 with the simultaneous generation (address bits 14-16 of the address word) of the command to activate the transfer synchronizer 30 / The selected information byte is entered into the front transfer register 11 the signal from the clock generator 23, and the transfer synchronizer 30 forts the wait signal for the microprocessor 20 (received at its third control input) during the entire transmission cycle of this byte. At the same time, the transfer synchronizer 30 forms the shift gates of the transfer register 11.

After one byte has been received, the wait signal is removed from microprocessor 20 and it selects the next byte of the transmitted packet. The process is repeated until the end of the packet is transmitted. Similarly, the transfer of the token and receipt is carried out. In the transmission mode, the network station 2 is set by the ACM to operate with the first transmitter 13, and the indicator 26 is not locked.

After issuing the information packet, the corresponding network station 2 transfers it, through some delay, generates and outputs a token allowing the work of the next one in the direction of transmission of the network station 2, which operates similarly

The information packet formed by one of the network stations 2 (and then the marker) through the corresponding first keys 4, splitters 5, amplifiers 6 and the second keys 15 of all network stations 2 is fed to the input of the first network station 1 (without delay of re-reception), which, in reception mode, operates in the same way as network station 2o. In this case, the information Pszhet and receipts from network stations 2 arrive through the second filter 57 to the second receiver 58, and the token and the receipt arrive at its input and through the first filter to the first receiver 35.

The need to introduce the second reception status indicator 59 is due to the fact (FIG. 4) that when the first network station 1 issues a receipt for the corresponding network station 2 confirming that it received a specified number of information packets or receipt of an error in receiving the information packet (which sent immediately after receiving the wrong packet)

6268

falls on the input of the first one from the -circuit station 1 and causes a distortion of the information packet currently being received. In addition, the receipt is intended only for the DNP of a specific network station 2, as a result of which it is not processed by the first network station 1.

Q In this case, upon receipt of information via the IC, it is set to 1 indicator 59, which blocks the operation of the first receiver 35 (CC). At the end of the reception of the information packet 5, the second indicator 59, as well as the first indicator 5, is reset to the initial state. With the same purpose, at network stations 2 during the issuance. chi information package in the channel with

0 communication is blocked by the receive status indicator 26.

The first network station 1 operates in the same way as network stations 2, with the exception of

25, the operation of setting the required transmitter, since the first network station 1 transmits only on the frequency of the control channel. After polling all connected

30 network stations 2 (which is determined by the receipt of a marker from the last one), the first network station I sends a marker for the next onpqca cycle to the communication channel.

When receiving a certain predetermined number of information packets, the first network station 1 sends it a confirmation receipt containing information about

The Q number of the last correctly received information packet (Fig. 4). If the packet is received incorrectly, the receipt is received immediately and this network station 2 repeats the transmission of the packet in the next cycle. Receipts are sent by the Criminal Code.

The configuration of network stations 2. for operating in a specific mode, as well as control information necessary for transmitting to the subscribers connected to them, are transmitted in the form of control-. packets containing the address of a specific network station 2 (FIG. 4). Upon receipt of this packet, it is copied to the memory of the OZB 18 and given out to the subscriber through block 19, and to the first network station 1, an IR receipt is issued on receipt of the correct

"about

package).

35

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In the second mode, the first network cTaiiu iH 1 can issue a marker for transmission not to the first of the connected network stations 2, but to a specific one from the entire set of station data. In this case, the marker indicates the address of the station to be polled.

The operation of the system blocks in this mode does not differ from that described for the first mode.

Thus, in comparison with the known message transfer system, the proposed base object of the proposed system makes it possible to increase the message transfer rate and system capacity by eliminating the overtaking of information in each intermediate network station.

formula of invention

The message transfer system, containing n serial strangions connected in series, the second input and output of which are connected respectively to the output and the input of each of the n interface blocks, each of (nl) network stations containing successively connected first and second keys connected receiver, receive register, data buffer, transfer register, to the inputs of which the information outputs of the permanent storage unit 5 are connected; information inputs and outputs of the operational storage unit; block transmitting and receiving a microprocessor, a switch and a first transmitter connected in series to a receiving end decoder, to the information inputs of which are connected to the outputs of the receive register, a receiving status indicator, to the second input of which the receiver output is connected, the reception synchronizer, the second output of which is connected to the control input reception register, address counter, address buffer, the outputs of which are connected to the address input of a permanent storage unit, an operational storage unit, a transmission and reception unit, and a The address outputs of the microprocessor, the address decoder, the second output of which is connected to the first control input through the transfer synchronizer via the transfer synchronizer.

five

626810

trigger mode, the first output of which is connected to the control input of the switch, and the interrupt unit, the first and second outputs of which are connected to the first and second control inputs of the microprocessor, to the third control input of which is connected the second output of the transfer synchronizer,

0 to the fourth and fifth manager

the inputs of the microprocessor are connected respectively to the output of the synchronizer reception and the first output of the clock generator, the second output of which is connected

5 to the second control inputs of the receive synchronizer, transmission synchronizer and transmission register, the third clock input to the clock input of the reception and transmission unit,

0 to the first and second control inputs of which the first and second outputs of the microprocessor are connected, the third output of which is connected to the first control input, the operational memory of the receiving unit and the third control input of the receiving-transmitting unit, and to the control input of the permanent storage unit through the element And, to the second input of which is connected

0 the third output of the address decoder, the fourth output of which is connected to the reset input of the address counter, the fourth microprocessor input - to the third control input of the synchronizer

5 reception, the first control inputs of the reception end decoder, the data buffer, the address buffer, and to the second control input of the random access memory, through the element

0 OR, to the second input of which the fifth output of the address decoder is connected, to the first and second control inputs of which the fifth and sixth outputs of the microprocessor are connected, and

5 the progress of the reception status indicator pod; xychen to the second input of the block, interrupt, the first of the n network stations contains the first receiver, the first and second connected in series

0 keys, a transmitter is connected to the second input of the latter, a receive register connected in series, a data buffer and a transfer register to the inputs of which information is connected

5 Permanent Memory Outputs

unit, information inputs and outputs of the operational storage unit, the reception-transmission unit and the microprocessor, connected in series

the reception end encoder, to the information inputs of which the outputs of the reception register are connected, the first indicator of the reception status, the second input of which is connected to the input of the reception register, the reception synchronizer, the second output of which is connected to the control input of the reception register, the address counter, the address buffer, the outputs of which connected to the address inputs of the persistent storage unit, the operative storage unit, the reception-transmission unit and the address outputs of the microprocessor, the address decoder, to the first and BTOpobfy control inputs to The first and second outputs of the microprocessor are expensively connected, and the transfer synchronizer, the first output of which is connected to the first control

transfer register input, to the second control input of which, the control input of the transfer synchronizer, the second control input of the reception synchronizer is connected to the first output of the clock generator, the second output of which is connected to the synchronization input of the transmission and reception unit, the third output to the first control input the microprocessor, to the second control input of which the first output of the reception synchronizer is connected, to the third control input of the microprocessor - the second output of the gear synchronizer Ie third and fourth in The microprocessor codes to the first and second control inputs of the receiving-transmitting unit, the fifth output to the third controlling input of the receiving-transmitting unit, to the first controlling input of the operational storage unit, and to the controlling input of the permanent storage unit through element And, to the second input of which

keys, the second output of the decoder address to the second input of which you connected

Sa, the third output of which is connected to the reset input of the address counter, the microprocessor's right output - to the third control input of the synchronizer

the course of the second reception status indicator is connected to the second input of the adder, while the fifth pass of the address decoder is connected to the second input

the reception, the control inputs of the buffer of the ad-Q interrupt block, and the output of the transfer register, the decoder of the reception end, the reduction, is connected to the input of the transmitter.

data bearer to the (first control input of the random access memory block) via the liJUl element, to the fourth input of which the fourth output of the address decoder is connected, to the fourth and fifth control inputs of the microprocessor, to the first input of the interrupt block, to the first input of which the connected the output of the first reception status indicator, which is 10 times so that 5 in order to increase the system capacity by reducing the recapture time, a second transmitter, filter, is inserted into each of the network stations (n-1) Whose output is connected to the receiver input, the second output of the first switch connected in series across the input branching Applicant, the second output of which is connected to the filter input amplifier and adder, and to the second inputs of which are connected TpeTbeNry sootvetst-

the output of the first transmitter and the second output of the switch through the second transmitter, is connected to the second input of the second key, while the second output of the mode trigger is connected to

To the control input of the first reception indicator, and in the first of the n network stations, a second reception status indicator has been entered, to the first input of which the output of the decoder is connected

termination of reception, the first filter, the adder, and the second output of the first key through the second filter introduced in series and the second receiver connected to the first input of the sum

the matora, the output of which is connected to the input of the reception register and the second input of the first reception status indicator, and through the first filter connected in series and the first receiver, to

the course of the second reception status indicator is connected to the second input of the adder, while the fifth pass of the address decoder is connected to the second input

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Claims (1)

Claim A message transmission system comprising η network stations connected in series in a ring, the second input and output of which are connected respectively to the output and input of each of the η interface units, each of (η-l) network stations containing the first and second keys connected in series, connected in series a receiver, a reception register, a data buffer, a transmission register, to the inputs of which are connected the information outputs of the permanent storage unit, the information inputs and outputs of the online storage unit, of a transmission system and a microprocessor, a switch and a first transmitter, a decoding end decoder connected in series to the information inputs of which the outputs of the reception register are connected, an indicator of the reception status, to the second input of which a receiver output is connected, a reception synchronizer, the second output of which is connected to the control input of the reception register , address counter., address buffer, the outputs of which are connected to the address inputs of the read-only memory, read-only memory, transmit reception unit and address Exit microprocessor, an address decoder, via the second output of which is connected to the synchronizer transmitting a first control input of the transmit register, 13 562.68 About 1 trigger mode, the first output of which is connected to the control input of the switch and the interrupt unit, per _{g of} vy and a second output of which cheny connected to first and second control inputs of the microprocessor, the third control input of which is connected a second output transmission synchronizer 10 to the fourth and the fifth control inputs of the microprocessor are connected respectively to the output of the receive synchronizer and the first output of the clock generator, the second output of which is connected to the second control inputs of the receive synchronizer, sync the transfer reducer and the transmission register, the third output of the clock generator is connected to the synchronization input of the receive-transmit unit, 20 to the first and second control inputs of which the first and second outputs of the microprocessor are connected, the third output of which is connected to the first control input, the operational memory unit and the third control the input of the transmit-receive unit, and to the control input of the permanent storage unit through the And element, to the second input of which 30 the third output of the address decoder, the fourth output of which is connected to the reset input of the address counter, the fourth output of the microprocessor - to the third control input of the synchronizer S ^ reception, the first control inputs of the decoder of the end of reception, data buffer, address buffer, and to the second control input of random access memory block - through an OR element 40, to the second input of which the fifth output of the address decoder is connected, to the first and second control inputs of which the fifth and sixth outputs of the microprocessor are connected, and the output and the reception state speaker is connected to the second input of the block, interrupts, the first of η network stations contains the first receiver, the first and second 5Q keys are connected in series, the transmitter is connected to the second input of the last, the reception register, the data buffer and the transmission register are connected to the inputs to which inputs are connected informational 55 outputs of a permanent storage unit, information inputs and outputs of an operational storage unit, a transmit-receive unit and a microprocessor connected in series to 1 1 reception end encoder, to the information inputs of which the outputs of the reception register are connected, the first indicator of the reception status, the input of the reception register is connected to the second input, the reception synchronizer, the second output of which is connected to the control input of the reception register, address counter, address buffer, outputs _1f which is connected to the address inputs of the permanent storage unit, random access memory unit, the transmit-receive unit and the address outputs of the microprocessor, an address decoder, _υ to the first and second control inputs which will be connected to the first and second outputs of the microprocessor, and a transmission synchronizer, the first output of which is connected to the first control _{2 |} the first input of the transfer register, to the second control input of which, the control input of the synchronizer, the second control input of the receive synchronizer, the first 2 output of the clock generator is connected, the second output of which is connected to the synchronization input of the receive-transmit unit, the third output is to the first control input of the microprocessor, the second 3 control input of which the first output of the receive synchronizer is connected, to the third control input of the microprocessor - the second output of the transfer synchronizer, the third and fourth the microprocessor moves to the first and second control inputs of the receive-transmit unit, the fifth output to the third control input of the receive-transmit unit, to the first control ₄ input of the operational storage unit, and to the control input of the permanent storage unit through the And element, to the second the input of which is connected to the second output of the address decoder — ₄ sa, the third output of which is connected to the reset input of the address counter, the sixth output of the microprocessor — to the third control input of the receive synchronizer, the control inputs of the buffer a d - ₅ res, the decoder of the end of reception, the data buffer, and to the second control input of the random access memory via the OR element, to the second input of which the fourth output of the address decoder is connected, the first and second outputs of the interrupt block are connected to the fourth and fifth control inputs of the microprocessor, to the first input of which the output of the first indicator of the reception status is connected, the reason is that, in order to increase the throughput of the system by reducing the reception time, to each of (p-1) network stations a second transmitter, a filter, the output of which is connected to the input of the receiver, a second output of the first key through a coupler connected in series, a second output of which is connected to a filter input, an amplifier and an adder, the second and third inputs of which are connected respectively to the output of the first transmitter and the second output of the switch through the second transmitter is connected to the second input of the second key, while the second output of the mode trigger is connected to O to the control input of the first reception indicator, and in the first of η ce of the second stations, a second reception status indicator is introduced, to the first input of which the decoder output is connected, ₅ ends of reception, the first filter, the adder, and the second output of the first key is connected through the second filter and the second receiver entered in series and connected to the first input of the sum — About the mater, output which is connected to the input of the reception register and the second input of the first indicator of the reception status, and through the first filter and the first receiver connected in series, to 15, the second input of which the output of the second reception status indicator is connected, is connected to the second input of the adder, while the fifth output of the address decoder is connected to the · second input, q interrupt unit ^ output of the transfer register is connected to the input of the transmitter.