SU1338088A1 - Device for digital transmission of sound signal - Google Patents

Abstract

This invention relates to the field of email. The purpose of the invention is to improve the accuracy of the sound signal transmission by reducing the distortion of the amplitude-frequency spectrum of this signal. The operation of the device on mutual compensation of amplitude-frequency distortions arising during processing on two interpolators of the zero order of the direct and inverse representations of the signal and their subsequent summation. Logic unit 8 provides, by controlling the multiplexers 7 and 12, alternately reading from the buffer registers 5-1 and 5-2 of the input information. At the time of the change of information in the indicated registers, the information recorded in the registers on the previous clock is read. Block 8 is implemented on the basis of a standard trigger with dynamic. impact on the synchronization input, which has two inputs and two outputs. 3 il. i (L 00 from 00 about 00 00

Description

The invention relates to electrical communication, in particular, to a technique for transmitting a digital signal, and can be used in digital broadcasting when coordinating mutually unsynchronized equipment.

The aim of the invention is to improve the accuracy of the sound signal transmission by reducing the distortion of the amplitude-frequency spectrum of this signal.

FIG. 1 shows a block diagram of a digital audio transmission device; in fig. 2 - diagrams of operation of the multiplication unit; in fig. 3 - diagram of the logical unit.

The time axis represents the values of parallel codewords, the magnitude of which is Sgi in 2 (allocated clock sequences of the associated digital streams, S g ,, and S (control; they are sequences for controlling multiplexers).

The device contains an input 1, a serial-parallel converter 2 of a code, a sync time latch 3, a first block 4 of buffer registers consisting of buffer registers 5-1 and 5-2, a switch 6, a first multiplexer 7, a logic block 8, an adder 9 , the second block 10 of the buffer registers, the state and; s from the buffer registers 11-1 and 11-2, the second multiplexer 12, the first 13 and the second 14 inverters, the first 15 11 second 16 multiplication blocks, parallel-to-serial code converter 17, output 18 digital audio devices, input 19 sync you asto- device.

Inverters 13 and 14 invert the spectrum. Each of the mentioned spectrum inverters is a circuit that changes the sign of every second signal reading, and is executed on a parallel register. The realization of inversion in the indicated blocks requires the presence of two inputs - informational and clocking.

Multiplication unit 15 provides a frequency shift by multiplying the signal by a harmonic signal with a frequency equal to half the difference between the sampling frequencies of the input and output streams. Block 15 contains a harmonic signal generator and a multiplication unit.

Logic block 8 provides, by controlling the multiplexer, alternately reading the incoming information from the buffer registers 5-1 and 5-2. At the time of the change of information in the indicated registers, the information recorded in the registers at the previous cycle is read. Logic block 8 is implemented on the basis of a standard trigger with dynamic effects on the synchronization input, which has two inputs and two outputs. The device is built on

5 mutual compensation of amplitude-frequency distortions arising during processing on two interpolators of zero order and inverse representations of the signal and their subsequent summation.

A digital signal is fed through bus 1 to the first input of converter 2, which converts a serial digital stream into a parallel one.

5 action of the control signals from the output of the synchronizer clock 3. From the output of converter 2, the signal is alternately entered into buffer registers 5-1 and 5-2 under the influence of signals

0 control from switch 6. The counting from buffer registers 5-1 and 5-2 is performed via the first multiplexer 7 under the action of command pulses from logic unit 8 in accordance with the output signal synchronization received via bus 19. Logic unit 8 prohibits the reading of new information at the time of its change in the buffer registers, in this case, the pre-shared information is read. From the buffer registers 5-1 and 5-2 interpolated signal through multiplexer 7 is fed to the first input of the adder 9.

The inverse of the interpolator branch is made on the buffer registers 11-1 and 11-2 and the second multiplexer 12. The signal to this branch is fed through the first digital inverter 13, and its reverse inversion is produced by the second inverter 14. To compensate for the shift in the spectrum of the signal that occurs during digital inversion in the case of differences in input and output digital streams, the signal from the output of the second inverter 14 is fed to the first multiplication unit 15, where it is frequency shifted by multiplying by

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31338088

the tin frequency of the difference in the frequency of the sparging of the input and output outflows.

From the output of the multiplier 15, the digital ignal enters the second input of the summator 9, where it is added from the signal of the signal level to the next 15 minutes at a time, then you are in at the top of the screen. but

scrap processed in the straight branch of interpol torus. The signal after adder 9 exceeds the original level. To normalize it, a multiplication block 16 is inserted. The received signal is converted in the converter 17 from a parallel code to a serial one. The operation of the inverter 14, multipliers 15 and 16, the adder 9 and the converter 17 occurs in accordance with the synchronization of the output digital stream.

Claims (1)

Invention Formula A digital audio transmission device containing a sync frequency selector, whose input is an information input of a digital audio transmission device and connected to the first input of a serial-parallel code converter, whose output is through the first block of buffer registers, to which the first and second clock inputs the second outputs of the switch connected to the first and Yes, the output of which is an output of a digital audio signal transmission device, characterized in that, in order to increase the accuracy of the audio signal transmission by reducing the distortion of the amplitude-frequency spectrum of this signal, a logic block is inserted into it, to the input of which the sync frequency separator output is connected through a switch, connected in series with the first inverter, to the clock and information inputs of which the outputs of the sync-frequency selector and 15 consequently-parallel converter are connected a, the second block of buffer registers, to the first and second clock inputs of which the first and second outputs of the switch, the second multiplexer, are connected, to the clock inputs of the chytor and clock inputs of the first multiplexer, the outputs of the logic block, the second ineve. ip, the first multiplication unit, the adder, to the second input of which the clock output of the first multiplexer is connected, and the second multiplication unit, the output of which is connected to the information input of the parallel-serial code converter, the clock input of which is connected to the clock inputs of the logic unit, adder, first and second blocks multiplier, second inverter and owner - the second information inputs of the first multiplexer, as well as parallel-35 input sync-frequency device serial converter co-digital audio transmission. l -BcmpoiHHtiu harmonic generator Xcutnajta / Yes, the output of which is the output of a digital audio signal transmission device, characterized in that, in order to increase the accuracy of the audio signal transmission by reducing the distortion of the amplitude-frequency spectrum of this signal, a logic block is inserted into it, to the input of which the output of the clock signal is connected connected in series the first inverter, the clock and information inputs of which are connected to the outputs of the synchascope frequency selector and a sequential 5 consequently-parallel converter A second block of buffer registers, the first and second clock inputs of which are connected first and second switch outputs, a second multiplexer, a clock input kytorogo and clock inputs of the first multiplexer connected to outputs of the logic block, the second invariant BEy. ip, the first multiplication unit, the adder, to the second input of which the clock output of the first multiplexer is connected, and the second multiplication unit, the output of which is connected to the information input of the parallel-serial code converter, the clock input of which is connected to the clock inputs of the logic unit, adder, first and second blocks multiplier, second inverter and owner - 0 five 0 Compiled by V. Panitsky Editor A. Makovska Tehred V. Kadar Proofreader V. But ha Order 4147/57 Circulation 638 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 FIG.