SU1330631A1 - Device for multiplication of complex numbers in modular code - Google Patents

Abstract

The invention relates to a computational, technical technique and can be used in high-speed fast Fourier transform processors for multiplying complex numbers by turning factors, as well as for obtaining the latter. The purpose of the invention is to reduce hardware costs. The goal is achieved by the fact that in a device for multiplying complex numbers in a modular code, containing an input register 12, an additional code generation unit 8 according to the modules of the number systems, multiplexers 7 and II, a group of deduction blocks 21, auxiliary registers 5.10 , 13 and 23, the division unit 29 auxiliary module, the modular adder unit 22, the interval index calculation unit 17 and the constants storage units 16 and 18, vg:) are auxiliary to the register Q rya 2A, 27 and 30, the multiplex unit 26 - ditch, block 15 schemes compare audio, with a multi- vhodovy Mmator 20, block 28 modular subtracters, zlementy OR 6,14 and members 19, 25 and 31 with the corresponding delay bonds. 2 Il. (L с: / - Lfl с 00 о О) 00

Description

1 i

The invention relates to computational to- ohics and can be implemented in fast-response fast Fourier transform processors to multiply the complex numbers by the rotation nt-s, as well as to obtain the latter.

The purpose of the invention is to reduce hardware costs.

Figure 1 shows the structural scheme of a device for multiplying complex numbers in a modular code; 2 a time diagram of the operation of the device.

The device for multiplying the complex numbers in the modular code (Fig. 1) contains the first 1 and second 2 information inputs, the input 3 of the constant number and the group of clock inputs A of the device, the first auxiliary register 5, the first element OR 6, the first block 7 multiplexers, an additional code generation unit 8 modulo the number system, a device output 9, a second auxiliary register 10, a second multiplexer block 11, an input register 12, a third auxiliary register 13, a second element OR 14, a comparison circuit block 15, a first storage block 16 onstant, interval calculating unit 17 the index number, the second storage unit 18 constant, the first delay element 19.

V, (X,., 1,1) g, (X., 1o, 1); Re (X ,, U, l), ..., R (X ,, lp, l), (I)

where r. (X., 1d, 1) | m -., - X, -W / nii |;

(x, .c.1) «0-k;

W is the constant number 21-t-lj,

l, elo, l ,. 1 e (oL-i,

L is the number of used complex 45 constants (turning factors);

ha (is a system of mutually X; eiO, ..., mj-l,

1, - but simple modules, with m, 2p +

, p is a fixed natural number, t, is an auxiliary module of t, 7, p, gcd (m4, m) -l, k-1, (i V (X, 1,, l) (X, le, l), ..., Rt (X, l, l),

where RJ (X ,, l, l) X; W / m ,,, ..., k;

X if X p

,HELL

m V - X, if X, p.

MI (L nHX.llJlllBl.lM CVMM llli) t O, G RUSH U

blocks 2 1 ummi) pycheto, block 22 m () luL1, H1,1x hummator, MOTRt pn.irt prnoMiU-aTCJii.ni.irt register 2), pjn (1gltr-P, iy pofncTp 24, second delay element 25 , the third block 26 multiplexers, the sixth auxiliary register 27, the block 28 modular 1Q subtractors, the block 29 dividing into an auxiliary module, the seventh auxiliary register 30, the third delay element 31.

15

The timing diagram of the operation of the device (figure 2) is given for the case when the number of bases varies from

before

 eight

which corresponds.

It shows the steps for each of the functional units of the device, during which they are not responsible for processing the real part of the desired complex number.

The time diagram of the operation of the device when processing the scraper part of the desired Tioj number is obtained from the given diagram by shifting the last one by two measures.

The first storage unit 16 of the constants is re-stored on the k-1 memory elements, in the cell i-ro of which the constants with the address X 2 2 are written:

 1, ..., k-l); k is the number of modules of the selected modular system of 1.1 numbers.

W- (

M

1, tc - (

M., / m; , M

V-

n

j

m.

The first, second and third address inputs of the memory elements together form the first, second and third address inputs of the constant storage unit 16, and the outputs corresponding to the first and –th components of the output residue sets form the first and jth outputs of the block 16, respectively. storage constants (j-2, ...,.). A block of constants is written to the cell of block 18 with address X + 1, -2 1:

(2)

The group of blocks 21 of the summation of residues contains the blocks of summation of residues modulo m, i - and from co- | the second (, 1, ..., k) carries out the statement for T logjk-l (cycles of sets I-k-1 of residues modulo m ,.

The block 17 for calculating the interval index of a number from an input modular code (x ,, ..., X |) of a certain number X of a modular number system determines the machine interval index:

I (x) - / i (x) / m, "- i. -f

m + ..

m.

-IM :;

where X ,, V., M. ,,, -Xj / m ,;

I (X) is the interval index of a number.

Comparison circuit block 15 contains k-l comparison circuits, each of which forms a single match on output if the value at the first input is greater than or equal to the value at the second input.

Block 29 of division into an auxiliary module is implemented on k memory elements, into the cell with the address v + 2 ° 1, the i-ro from which the deduction is written

The first inputs of all the memory elements are combined and together with the second inputs form the input of block 29 and an auxiliary module.

k-

„V, C / iJc.l-W l

de Q, - I ----- J;

KA W - А W) - 21 (р;) + QVVQ; - I, ;

fi1 and

k-t

KA W - A W) - L (Q f, qV)

D f, -l --- - -

. "VM- -i7 - l

 ; “I (A) W, .I (A) W

 ) W; (-A) .W;

i, is the number of overflows when adding the numbers A W and A flj is the number of overflows when adding the numbers A W and A W. Consider how the device of multiplication of complex numbers in the mouse code works.

On the first and second 4 groups, the output of the element 31 delay signals equalizing 6

The modular code (.45 of the part A of the number A, for the first information of the first block 7 mule control input to 50 sig and, 0, write register 12; and in reg 3 devices of the transfer constant W

In the first cycle 55 (o l.., Oi) of the solution via the second multiplexers () in the dex calculation block 17, the numbers and perms

.

-

15

Elements 19 and 31 of the hall (p n n) perform a delay of the signal according to the heating of the T and (T + 3) measures.

The second delay element 25 is a chain of T-I serially connected registers, the flow of the first and the output of the last of which are input 10 and the output of the second delay element 25, respectively.

The multiplication algorithm of complex numbers implemented by the proposed device is based on the following.

Suppose you want to multiply the complex .1. . (I number A A jA on the complex

„W .W

constant 1-- having

pMk-1, PMl,.,

Number 1, A, A, W, W are integers from the D range of the modular number system. I

The real and imaginary parts of the product JB can be computed using the following approximation} formulas:

in g J (A W - A W);

in J CA W -t- A W), (3)

where J (X) l (X) / mj is the nuclear interval index of the number X;

x is the nearest x integer. Wherein

20

25

thirty

(6)

On the first and second clock inputs of 4 groups, the output of the OR element 1A and the delay element 31, the control signals 6p-6 ,, are formed.

The modular code (o ,,..., (Y 1) imaginary .45 part A of the number A, coming from the second information input 2 of the device to the first information input of the first block 7 multiplexers, to the control input of which 50 sigal and , 0, is written to the input register 12; and the complex constant number W is transmitted to the register 13 via the device input 3.

In the first cycle, the modular code 55 (o l., Oi) A from the input 1 of the device through the second block II multiplexers () is fed to the input of the block 17 for calculating the interval index of the number and the first address input

513

the first block 16 hrshkmsh kppst nt, on the second and third pdrssiie ihodm with the output of respectively S1I 6 element and register 13 will receive the values 1 and 1,

0

At the first output of the first storage unit 16, constants, a set of residues r ("., 1 d 1), which enters the auxiliary register 2A, is formed; at the JM output of the first storage unit 16, constants, a set of residues R. (p., IO. D (see, formula (1), which enters the input of the group of blocks 21, the summation of deductions, which during the next T cycles add modules of input residues modulo the system, and the interval calculation unit 17 of the number index begins calculation modulo t, interval interval 1 (L).

In the second cycle of operation of the device, the modular code (o ,.,., D () of the number A from the output of the input register 12 through the second block 11 multiplexer ("l.)" Goes to the input of the interval calculating index number 17 and the first address input of the first block 16 storing constants, the second and third address inputs of which receive the values 1 and 1 (, 1- The contents of the auxiliary registra 2D are written to the auxiliary register 27 and the auxiliary register 24 receives the set of counts G; (dJ, 1,1), which formed at the first output of the first storage unit 16 nstant.

At the J-M output of the first storage unit 16, constants, a set of residues Rj .j (, Ij,) is received at the inputs of the residue addition units 21, and the interval index calculation unit 17 starts the calculations modulo m, interval interval 1 (L).

In the third cycle of operation, the contents of the auxiliary registers 24 and 27 arrive respectively at the first and second inputs of the block I5 of the comparison circuits, at the output of which comparisons are formed pesyJibraTbi, which arrive at the fourth cycle at the input of the adder 20, which finds the religion Q that is written to the first register the second element 25 of the delay.

On the (T-1) -th link, the input of the reception of the register code 23 receives a signal i ;, l, following which the contents of register 1 of the 13 rd code in the register 23

, 3i6

j b ist "1G Iii () of the work cycle of the system - P n ic i-iin on ibtxonc: block 17 of the computation iiM t e) of the 1st index of the number of forms 1) per test 1. (A).

At the () th cycle, the value of I (A) from the output of the block 17 for calculating the interval index of the number goes to the first address input of the second block 18 of storing constants, to the third and second

the address inputs; 1s of which are fed respectively to the values from the output of the delay element 19 and the value 1 from the output of the register 23. At the output of the second storage unit 18 of the constants, a set of residues is formed modulo Qy (formula (7), which is written to the auxiliary register 5 .} 1a n (, on the input of the group of blocks of 2 summation of residues, a set of calculations is formed

k-i

(one

2 „And, Ch.

u i

and on in, on the go of block 17 for calculating the differential index of a number - the deduction

l (I

I (L).

h

The LD (T--2) -th step of the magnitude from the outputs of the 1-rttt block 21 summation and t-helper) of register 5 is received respectively on the first and second

the inputs of the modular adders block 22, at the output of the device O with a full-i T

Auxiliary register 30. At the same time, the value from the output of the I7 calculation unit of the interval index of the number is fed to the first address input of the second constant storage unit 18, to the third and second addressc- (

Z-Q. writing down i f

The values of which are supplied respectively with the value of 1 "from the output of the delay element 19 and 1 from the output of the register 13. On the output of the second storage unit 18 of the constants, a set of residues is formed modulo I (A) -W, which is written to the auxiliary-Hbrii register 5. At the output of the group of blocks of summation of residues, a set of residues is formed modulo wind I.

t 1 is the second delay element 25;

At the () -th step, the values from the outputs of the group of blocks 21 of the summation of residues and the auxiliary register 5 are supplied to the first and second inputs of the modular sum block, respectively.

at the exit

tori 22, on H1. which form1H1 is the value of X

-I 1, j

 I (A) W), which takes the PO in auxiliary register 30. The previous contents of the auxiliary register 30 (X) are fed to the first (, w input of the modulator subtractors unit 28, to the second input of which through the third block 26 multiplexers (y, 0) - the stroke of the second delay element 25 is supplied with the value S7. The modular subtractors unit 28 finds the value YX, which is written to the auxiliary register W.

At the () th device cycle, the value of Xj from the output of the auxiliary register 30 is fed to the nepBbrfi LOD

unit 28 modula. hx subtractors, the second input KOTOpoi o through unit 26 multiplexers () from the output of the auxiliary register 10 receives the value Y. The modular subtractors block finds the value X - Y –KA W -) (see formula (6), which is written to the auxiliary register 10.

On the (T - "- 5) th cycle, the contents of the auxiliary register O are fed to the input of the division unit 29 into the auxiliary module defining the module ньh code (pj,.,., F,) of the real part of the desired drive, which is removed from output 9 of the device.

During the cycles with the third ps (T-7) inclusive, the specified actions are performed for modular codes

(;, ...,;) and (, .....

(-c (/ ha). the last of which, on the third cycle of the device operation, is formed in block 8 of forming an additional-pin code by the input modular code of the number A and is written to the input register 12. The modular code (..... / ijl ) at the () th cycle it is removed from the output 9 of the device and with this the multiplication of the complex numbers A and W is completed.

Claims (1)

Invention Formula A device for multiplying complex numbers in a modular code, containing an input register, an additional code generation unit modulo the number system, two multiplexer units, a group of summation units NFU nhineiOH, ČR GY (ICHICH i l, 1 l G .sh.i:: h PCM ISTRL, BDIK DELCHIC ICHW; N-N.M - TOJibHi m module, Mo block; i.y.iibin.ix, chtor, block T NUMBER 7P - | p 1. 1YUGH (1 the index of the number and the bottom of the block. a., l iichm- nye inputs of the first and ptorog Plock multiplexers sordineiy chi tnetst0 iepnp vtort- with OA and the first inputs ormltsiop- ustrO1) stvl, P1.1HCHL psrpo- th block multipprkgoron sosdinoi input to the input register, which is connected t.rsod with an input of a block of form 5 ropaps of additional code about the modules of the number system, the output of the second 1–0 multiplexer block of the network (with the first address input of the first constant storage unit, the outputs of which 0 except the youngest one, connected to the inputs of the corresponding sum-puncing unit of the group, the outputs of which are connected to the input of the first addendum of the modular adders unit, the input of the second addend of which is connected to the output of the second auxiliary storage unit . The first 1 address input is connected to the yen with the output of a flea. The calculation of the interval index of the number whose input is connected to the output of the second multiplexer unit, the output of the second auxiliary register is connected to 5, the input of the dividing unit to the auxiliary module, the output of which is the output of the device, the input of the number of the device constant connected to the input of the third auxiliary register, The output of which is connected to the information input of the fourth auxiliary register, the outputs of the third and fourth auxiliary registers are connected respectively to the second address inputs of the first and second blocks of storing constants, the first and second clock inputs of the device group are connected respectively to the enable input of the fourth auxiliary register and with the control input of the first multiplexer unit, characterized in that. that, in order to reduce hardware eratrates, it contains the fifth, sixth and seventh 5 auxiliary registers, the third block of multiplexers, the block of comparison circuits, the multi-input adder, the block of modular subtractors, two 11PI and elemos. three delay elements, Fri 913 The additional code generation unit is connected to the second information input of the first block to the multiplexers by moduli of the number system; the output of the input register is connected to the second information input of the second block of cultivators, the lower output of the first storage unit of the constants is connected to the input of the fifth auxiliary register whose output is connected to the first input of the comparison circuit block and through the sixth auxiliary register - with the second input of the comparison circuit block whose output is connected to the second input of the multi-input sum Ator, the first clock input of the device group is connected to the first inputs of the first and second OR elements, the output of the first OR element is connected to the third address input of the first storage unit of constants and through the first delay element to the third address input of the second storage unit of constants, the output of the second OR input with the manager 3110 the input of the second multiplexer unit, the second and third clock inputs g of the device handle are connected respectively to the second inputs of the first and second OR elements, the output of the multi-input adder is connected to the input of the second delay element, the output of which is connected to the input information input the third multiplexer unit, the second information input of which is connected to the output of the second auxiliary register, the output of the second element OR is connected through the third element delays with the control input of the third multiplexer unit, the output of which is connected to the input of the readable unit of modular subtractors, the bypass of which is connected to the input of the second auxiliary register, the output of the modular adders block is connected to the input of the seventh auxiliary register, the output of which is connected to the input of the modular reduced block subtractors. 7 2J "5678 P P P Editor M.Dshyn 2 Compiled by A. Klyuev Tehred c. Kadar Proofreader I. Muska Order 3583/50 Circulation 672 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 P