SU1310755A1 - Device for checking logic units - Google Patents

Abstract

The invention relates to instrumentation technology and can be used to control logic blocks. The purpose of the invention — extending the functionality — is achieved by controlling the byte of information and storing its value in failed situations. To do this, a device containing a shaper 6, a display unit 4 and a trigger 7, additionally includes a repeater unit 1, a memory unit 2, a information output unit 3, a control unit 5, a resistor 8, an LED 9 and a reset button 10, and as a trigger 7 used JKRS trigger. The device is able to memorize an erroneous byte in memory block 2, indicating its status by block 4. This state of the device is maintained until the memory block 2 and trigger 7 are reset with the help of button 10. 6 Il. i (L figure 1 Vf / r

Description

one

The invention relates to instrumentation technology and can be used to control logic blocks.

The purpose of the invention is to expand the functionality of the device by allowing the byte of information to be monitored and its value stored in error situations.

Figure 1 shows the block diagram of the proposed device; Fig. 2 is a block diagram of a repeater unit; Fig. 3 is a block diagram of a memory block; FIG. 4 is a block diagram of the information block; Fig. 3 is a block diagram of the display unit; figure 6 - block diagram of the control unit.

The device contains a repeater unit, memory block 2, information block 3, indication block 4, control block 5, driver 6, JKRS trigger 7, resistor 8, LED 9 and button 10, the device input connected by a code line to the input of block I repeaters, the output of which is connected to the code line. to the input of the control unit 5, to the first input of the memory 2 and to the first input of the information block 3, the second input of which is connected to the output of the memory block 2 by the code line, and the output to the input of the display 4. The first output of control unit 5 is connected to the second input of memory 2 and to the S input of the trigger 7, and the second output to the first input of the imager 6, the output of which is connected to the third input of memory 2 and to the C input of the trigger 7, R- the input of which is connected to the fourth input of the memory block 2 and through the button 10 with the zero potential bus. The zero output of the trigger 7 is connected to the second input of the driver 6 and through a resistor 8 to the cathode of the LED 9, the anode of which is connected to the power bus.

The repeater unit 1 contains the resistors P-14, the transistor 5, the inverter 16, the element 2И-НЕ 17, the LED 18 and the repeaters 19.1 - 19.9.

Repeaters 19.1-19.9 are necessary in order to exclude the possibility of failure of the test of logic elements with limited load capacity.

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The zero input (channel) of the repeater unit 1 is also connected to the base of the transistor 15 and through the resistor 11 to the power supply bus, as well as through the resistor I2 to the zero potential bus, to which the emitter of the transistor 15 is connected through the resistor 13, which in turn is connected I6 inverter with the first input element

2I-NOT 17, the second input of which is connected to the zero input of the block 1 of the repeaters, and the output of the element 2I-NOT 17 is connected through the resistor 14 to the cathode of the LED 18. The anode of the light-coil 18 and

the collector of transistor 15 is connected to the power line. The described circuit is intended to determine and indicate the logical state of the break. Memory block 2, block diagram

which is shown in FIG. 3, made in the form of a set of nine JKRS-flip-flops 20.1-20.9, the first P-inputs of which are connected to the outputs of the repeater unit 1. The second J-inputs of the trigger 20.120 .9 are combined, they are supplied with the potential Error generated by the control unit 5. The combined inputs of the triggers 20.1-20.9 impulse is given Record formed by the driver

6. The combined R-inputs of the flip-flops 20.1-20.9 through the button 10 Reset are connected to the ground potential.

The information output unit 3, the structural scheme of which is shown in FIG. 4, consists of a set of nine elements 2-2AND-OR-NOT 21.1-21.9, - with the first inputs of the first circuits 2I elements 2-2-OR-NOT 21.1-21.9 are connected

with the outputs of the repeater unit 1, and the second inputs are combined and connected to the first contact of the switch 22. The first inputs of the second circuits 2I elements 2-2I-RSHI-HE 21.1-21.9 are connected

with the outputs of the memory block 2, and the second inputs with the second contact of the switch 22, the third contact of which is connected to the zero potential bus. Thus, depending on the position of the switch 22 Memory - A probe to the output of the block 3, information passes either from the outputs of the repeater block 1 or from the outputs of the memory block 2, which provides

the possibility of using the device for analyzing the state of nine logical circuits as in static mode (for example, when searching for

equality of the computer in the tact mode of operation), and in the dynamic mode when detecting faulty situations.

The display unit 4, the block diagram of which is shown in FIG. 5, contains a set of nine LEDs 23. - 23.9, the anodes of which are connected to the power bus through resistors 24.1-24.9. The cathodes of the LEDs 23.1-23.9 are connected to the outputs of the information output unit 3.

The control unit 5, the block diagram of which is shown in FIG. 6, consists of a modulo 2 convolution element 25, three 2I-NO 26-28 elements and two inverters 29 and 30. Information bits of the controlled byte from the block outputs are supplied to the inputs of element 25. 1 repeaters. The first output of element 25 Odd is connected to the first input of element 2И-НЕ 26, the second input of which is connected to the output of the check bit of black 1 repeaters and through an inverter 29 to the first input of element 2И-НЕ 27, the second input of which is connected to the second output of convolution element 25 modulo 2. The outputs of the elements 2И-НЕ 26 and 27 are connected to the inputs of the element 2И-НЕ 28, the output of which is connected to the first output of the control unit 5 and through the inverter 30 to the second output of the unit 5.

The device works as follows.

Information about the state of the controlled byte through the repeater unit 1 is fed to the inputs of the information output unit 3, the memory unit 2, and the control unit 5. If the device is in the Probe mode, which is set by the switch 22 in the information output unit 3, the unit 3 passes information into the display unit 4 directly from the repeater unit 1. The on state of the LEDs 23.1-23.9 in the display unit 4 corresponds to the single state of the corresponding bit of information in the byte, the off state to the zero one.

Thus, the device makes it possible to observe changes in logical levels simultaneously in nine chains.

If the device is in the Memory mode, the information through the information output unit 3 passes to the input of the display unit 4 already from the output of the memory unit 2. Every input byte

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is analyzed by control unit 5, which in the case of arrival of a byte with incorrect parity, i.e. the number of bits in a byte and

the control bit is even; it triggers a signal-Error at its outputs, and at the first output this signal has a single level, at the second - zero. A differential from one to zero from the second output of the control unit 5 starts the shaper 6, which generates a pulse, on the falling front of which the trigger 7 is set to the single position, so

as at the J-input of the trigger 7 at this moment there is a resolving unit potential Error from the first output of the control unit 5. Simultaneously wrong byte and test bit,

Those arriving at the first J-inputs of the flip-flops 20.1-20.9 are memorized in memory block 2, since the second J-inputs of the flip-flops 20.1-20.9 contain the resolving unit potential Error from the first output of the control unit 5, and the C-inputs of the flip-flops 20.1 -20.9 the synchronizing impulse comes from the driver 6 output. Zero potential from the inverse trigger output,

7 causes the LED to glow 9,

signaling a crash. In addition, the zero potential from the reverse output of the trigger 7 post-falls to the second input of the forwarder 6, preventing its further operation. This is necessary in order to eliminate the possible corruption of information in memory block 2 when a subsequent byte of the wrong parity appears at the output of the device.

The duration of the pulse generated by the shaper 6 is chosen equal to half the pulse duration of the clock frequency generated by the computer generator. This is necessary to avoid possible false tipping of the trigger 7, since the information bits can arrive with a certain phase shift, which is associated with different switching times of various kinds of registers and counters, with different delay times introduced by cable receivers and relays.

sensors, etc. The phase shift of the information bits may cause false bursts at the outputs of the control unit 5 and, accordingly, the start of the driver 6, but the triggering of the trigger 7

does not occur, since the installation of the trigger 7 takes place on the falling edge of the pulse from the driver 6 arriving at the C input of the trigger 7, and the duration of this pulse is longer than the duration of the possible bursts, i.e. at the time of the end of the pulse from the forcing 6, there is a zero inhibitory potential at the 3 input of the trigger 7.

Thus, the device is capable of storing an erroneous byte in the memory block 2, indicating its status by the display block 4. Such a state of the device is maintained until the memory 2 and the trigger 7 are reset by the 10 Reset button.

Claims (1)

Invention Formula A device for controlling logical blocks, comprising a driver, an indication unit and a trigger, which is based on the fact that, in order to expand its functionality, a repeater unit, a memory unit, and a new information block are inserted into it. The control unit, the button, the resistor and the LED are used as a trigger, the device input is connected by a code line to the input of the repeater unit, the output of which is connected to the first input of the information block, to the input of the control unit and the first the input of the memory unit, the output of which is connected to the second input of the information output unit by the code line, the output of which is connected to the input of the display unit by the code line, the first output of the control unit is connected to the second input of the memory unit and with the J input of the trigger, and the second output with the first input of the driver, the output of which is connected to the third input of the memory unit and to the C input of the trigger, the inverse output of which is connected to the second input of the driver and connected in series with the resistor and LED and the R input of the trigger is connected to the fourth input of the memory unit and to the first contact of the button, the second contact of which is connected to the zero potential bus. FIG. H / 7OAff / r7 I f, f " J / ffffHC / H -L. fi &.