SU1305693A2 - Microprogram multiplexor channel - Google Patents

Abstract

The invention relates to computing, in particular the organization of firmware multiplex channels of firmware computers, and can be used to organize the exchange of information between peripheral devices and the processor. The aim of the invention is to extend the functionality of the firmware multiplex channel by organizing a floating number of subchannels and their arbitrary distribution. The microprogram multiplex channel contains a block of 2 registers, a block 6 of generation of control signals, a block 1 of decryption of commands, a block of switching 5, a block, 7 of analysis, a convolution node 9 modulo two, a block 14 of encoders 12, a node 15 of registers, a node 16 of decoders, node 17 commit subchannels, two registers 3 and 4, four groups of elements And 10-13, the element is NOT. 1 hp f-ly, 13 ill., 1 tab. yy to a C OS ate about: its OS H 23 I4J

Description

The invention relates to computing, in particular, to the organization of microprogram multiplex channels of microprogram computers, can be used to organize the exchange of information between peripheral devices and the processor, and is an improvement of the invention according to the author. No. 1256036.

The purpose of the invention is to expand the functionality of the microprogram multiplex channel by organizing a floating number of subchannels with the possibility of their arbitrary distribution, i.e. assigning any subchannel to any peripheral device — followed by its release after the end

communication channel with a peripheral device-20 information output 41 block register,

Fig, 1 shows a diagram of a firmware multiplex channel; in fig. 2 shows a block for decrypting commands; in fig. 3 - block registers; in fig. .4 - switching unit diagram; in fig. 5 is a block diagram of the control signal generation unit; Fig 6 is a diagram of the analysis block; on -fig., 7, a diagram of the block of encoders; in FIG. 8 is a schematic of the register node; Fig, 9 is a diagram of the node decoders; Fig, 10 is a diagram of the node fixing subchannels; in fig. 11 and 12 is a diagram of the algorithm for transferring a byte from the subscriber to kanggsh at the initiative of the subscriber; Fig. 13 shows the possible number of cells used in the processor's local memory when allocating subchannels.

11program multiplex kan; zl (Fig. 1) contains a command 1 decryption command, block 2 registers, registers: the second 3 and the first 4 block 5 comg, 1 mutations, block 6 generating control signals, block 7 analysis, 45 element HE 8, node 9 convolutions by mod., Two, four groups of I elements: fourth 10, third 11, second 12 and first 13, block 14 encoders, register node 15, decoder node 16, 50 subchannel fixation node 17, subscriber information output 18, input 19 inc power supply, CPU 20 clock output, information output 21

Switching unit 5 (FIG. 4) contains an element NOT 66, two groups of elements AND 67 and 68, a group of elements OR 69.

The control signal generation unit 6 (FIG. 5) contains an element AND 70, the first 71, the second 72 and the third 73 elements S1I, the second 74 and the first 75 elements NOT, the convolution node 76 modulo two.

Analysis block 7 (Fig. 6) contains

processor control output 22 abo- 55first 77, second 78, third 79 and

ntah, control input 23 subscriber, the fourth 80 elements NOT, the third 81,

information input 24 subscribers, the first 82, the second 83 and the fourth 84

Formation input 25 processor, And-elements, first 85 and second 86

formational. input 26 block switching elements OR.

the first information output 27 of the switching unit, the second information output 28 of the switching unit, the first control input 29 of the switching unit, the first output 30 of the group of information bits of the register block, the first output 31 of the group of control bits of the register block, the first output 32 of the block generation, control signals, second output 33 of the control signal generation unit, second output of the analysis unit, second input 35 of the analysis unit, third output 36 of the analysis unit, second output 37 of the group of control bits of the register block, output 38 e the element is NOT, the second output is 39 groups of information bits of the block of registers, the output 40 is a convolution node modulo two, the second

ditch, processor pause output 42, third output of command decryption block 43, first output of command decryption block 44, first output of block 45

analysis, the fourth output 46 of the command decryption unit, the information output 47 of the fixation node, the information output 48 of the encoder block, the second information output 49 and the first information output 50 of the register node, the information output 51 of the decoder node.

Block 1 decryption commands (Fig. 2) contains the register 52 of microinstructions and the decoder 53 microinstructions. The decoder 53 micro-commands has outputs 54-58.

The register block 2 (FIG. 3) contains the subsynchronization register 59, the reception register 60, the group of elements AND

61, register 62 in steps, D-flip-flop 63, first 64 and second 65 registers.

Switching unit 5 (FIG. 4) contains an element NOT 66, two groups of elements AND 67 and 68, a group of elements OR 69.

The control signal generation unit 6 (FIG. 5) contains an element AND 70, the first 71, the second 72 and the third 73 elements S1I, the second 74 and the first 75 elements NOT, the convolution node 76 modulo two.

Analysis block 7 (Fig. 6) contains

3-1305693

The encoder block 14 (FIG. 7) contains the first 87, the second 88, the third 89 and the fourth encoder 90, the first 91, the second 92 and the third 93 multiplexers and the fifth encoder 94. The multiplexers, and the fifth encoder, have outputs 95-97 ( Fig. 7).

The register node 15 (FIG. 8) contains the first 98 and second 99 single-bit registers, the first 100 and second 101 fO two-bit registers, the first 102 and second 103 three-bit registers, the group of elements AND 104. Registers 102 and 103 have outputs 105 respectively and 106 (Fig. 8).

Node 16 decoders contains the first 107 and 108 second decoders and element 109.

Node 17 commit subchannels contains a register 110 and a group of elements And 111.

The command decryption unit 1 is used to receive from the information output 21 microcommands to the microdiagnostics register 52 or through the group of elements AND 13 to the information input 25 of the processor to control the information transmitted from the processor to the output register 62 by comparing it in the processor and through the second register 3 on information input 24 of the subscriber in the case of transmitting information to the subscriber, receiving control signals for the subscriber from the information output of the processor 21 to the trigger 63, the first 64 and second 65 registers and issuing the control x signals from the trigger output 63, the first and second outputs of the first register 64 and the first and second outputs of the second register 65 to the information output 30 for issuing control signals to the subscriber through the first register 4 and to the control signal generating unit 6 20, issuing from the third output of the register 60 of receiving the control signal to the processor pause input 42, for arranging the reset of the second register 65

f5

mandates and microinstructions decoding with the 25g signal from the control input of the descrambler 53, first, second, ca, issuing control signals from

The third and fourth outputs of the third and fourth outputs are the result of the decryption of the 64-mic to the control output 31. The information writing commands to the register. Switch unit 5 is used

62 of the above, recording information in the trig 30dl switching information with the control of ger 63, the first register 64, the second re-output 22 subscribers through gruppistr 65, diagnostics, on which the elements 68 and the group of elements

writing information from re-OR 69 into subsynchronization register 59 is permitted

the hister 62 is dispensed through a group of elements in an operating mode or information from retows AND 67 to the register 59 subsynchronization — 35gistr 62 through a group of elements, and a reading on which the valve-tone AND 67 and a group of elements OR 69 are group elements AND 10 - 13 and information from them goes to information output 25 to the processor.

„40

The block / registers is intended for

receiving information from the subscriber to the group of elements I 61 from the information output 18 subscriber and sending information to the first input of the group of elements of the cops NOT 74 and 75 ,; coming through. And 10, receiving information from the information input 35 into the analysis block 7, the necessary output 27 to the subsynchronization register 59 and then receiving this information to the receiving and issuing register 60 from the first, second, third.

register 59 subsync in diagnostic mode.

The control signal generation unit 6 serves to generate some control signals necessary for controlling the operation of the channel equipment, namely signals with evil 50

to control the operation of peripheral devices, namely, signals from the elements OR 72 and 73, arriving at output 33 and then through register 4 to the control input 23 of the subscriber, as well as to be able to control the comparison in the processor, information received from information output 21 processes - cs pa, firstly, in the register of the first, the information from which comes through the second register 3 to the information input 24 subscribers in the form of the exchange data byte from the peripheral device fourth and fifth outputs of the register 60 reception to the information output 39, and from the first second, sixth and seventh outputs to output 37, receiving information into register 62 from information output 21 of the processor and information from output from register 62 through switching unit 5 into register 59 of subsynchronization in case

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diagnosing or through a group of elements And 13 to the information input 25 of the processor for organizing control of the information transmitted from the processor to the issuance register 62 by comparing it in the processor and through the second register 3 to the information input 24 of the subscriber in the case of transmitting information to the subscriber, receiving control signals for the subscriber from the information input processor 21 to the trigger 63, the first 64 and second 65 registers and issuing control signals from the output of the trigger 63, the first and second outputs of the first register 64 and from the first and second you one second register 65 to information output 30 for issuing, via the first register 4, control signals to the subscriber and to the control signal generation unit 6 0, issuing a control signal to the processor stop input 42 from the third output of the receive register 60, in order to arrange a second reset register 65

five

tone And 67 and group of elements OR 69

cops are NOT 74 and 75; coming through. input 35 to analysis block 7 required

register 59 subsync in diagnostic mode.

The control signal generation unit 6 serves to generate some control signals necessary for controlling the operation of the channel equipment, namely, signals from the HE elements 74 and 75 ,; coming through. input 35 to analysis block 7 required 0

to control the operation of peripheral devices, namely, signals from the elements OR 72 and 73, arriving at output 33 and then through register 4 to the control input 23 of the subscriber, as well as to be able to control the comparison in the processor, information received from information output 21 processes - cs pa, firstly, in the register of 62 steps, information from which comes through the second register 3 to the information input of 24 subscribers in the form of an exchange data byte with peripheral devices 15

CTB.aMHj a also for controlling the comparison in the processor through the group of elements And 13 to the information input 25 of the processor and, secondly, to the flip-flop 63, registers 64 and 65, from the outputs of which the information goes to the control formation block 6 signals, where this information goes from outputs 30 and 31 to element 76 to form a check-jQ th bit for this information and output 32 together with a control bit from element 76 and through a group of elements I 12 to information 25 processor input.

The analysis block 7 is used to generate control signals from the output of the element 81 and from the element 80, which through the outputs 45 and 34 are fed to the reset input of the register 65 and to the second input of the element 70 and, respectively, in order to exclude the microprogram analysis most frequently involved in the control control signals, which reduces the amount of channel firmware and, consequently, 25 the time of their execution, as well as the formation of a certain combination of control signals received from the outputs of the elements OR 85 and 86, which are received in percent via the JQ group of elements 11 and 11, after the analysis of which by microprogramming, the channel firmware determines the state of the three control signals, due to

20

which reduces the amount of channel mics, but the first, second, and third address

roprograms and, therefore, their execution time.

The HE element 8 is used to invert the synchronization signal received from the synchronization input 20 of the further use of the forward and inverse synchronization signals to control the reception of information in the register 59 and 60 of the register 2 and to generate a control signal at a certain time from the output of the element 81 in the block 7 analysis.

Modulo two convolution node 9 serves to form a control

40

the outputs of the diggers 87-90, and the outputs from the outputs of the multiplexers 91-93, from the address and control outputs of the tuner 94 to the information output 4 of a block of three-, two- and single-bit codes, respectively.

Register register node 15 is used to store information received from information input 48 on registers 98-103, as well as to output information from registers 98-103 through a group of elements 104 controlled by a control signal from outputs 54 received from a decoder 53

bit to the information that post- Q first information output 49 and with

It goes to its input from block 7 of analysis and block 2 of registers, respectively, and this test bit to the first input of the group of elements I 11.

Groups of elements 10-13 are used for switching with the help of a control signal from the output 44 of the decryption, information coming from block 2. registers from the outputs of registers 102 and 103 to the second information output 50.

The decoder node 16 is designed to form the corresponding cc stanta by decrypting three-bit information received on the inputs of the decoder 107 and 108 from the information input 50 and decrypt these constants through the information decoder 107 and 108.

the progress of the group element I 61 to the first input of the fourth group of elements AND 10, block 2 of registers from the output of register 60 of reception through information output 39, from block 7 of analysis from the elements OR 85 and 86 and from output 40 to the first input of the third group of elements 5

5 Q

comrade 1 1

block 6 of the formation with the first input of the second group AND 12, from block 2 regist0

of

The code 32 for the elements from the register output 62 to the first input of the first group of elements is And 13, followed by the simultaneous output from the outputs of the groups of elements And 10-13 of information to the information input 25 of the processor.

The encoder unit 14 is designed to form the address of a free subchannel, which is performed by analyzing the presence of zero bits in four bytes of the information word coming from the information output 21 of the processor byte-bye to the information inputs of the encoders 87-90, and forming the first zero bit in the information word , starting, for example, from the zero bit, using the fifth encoder 94, the first — fourth information inputs of which receive control outputs from the encoders 87–90, respectively, and using three mules Toleplexers 91-93, on the first - the fourth information inputs of which are received accordingly

0

the outputs of the diggers 87-90, and the outputs from the outputs of the multiplexers 91-93, from the address and control outputs of the drawer 94 to the information output 48 of the block of three-, two- and single-bit codes, respectively.

The register node 15 is used to store the registers 98-103 of information received from information input 48, as well as output information from registers 98-103 through a group of elements 104, controlled by a control signal from outputs 54 received from the output of the decoder 53, on

first information output 49 and with

the outputs of registers 102 and 103 to the second information output 50.

The decoder node 16 is designed to form the corresponding constants by decoding the three-bit information received at the inputs of the decoder, 107 and 108 from the information input 50 and decrypt these constants through the information inputs 50 and 108.

the group element And 109 under the control of the control signal from the input 57, obtained from the output of the decoder 53, to the information output 51,

The latching node 17 is designed to set using the switching register 110 of a specific number of subchannels by dialing with a switch a specific code on the switching register 110 and issuing this code through the I 111 group element under the control of the control signal 58 received from the output of the decryptor 53 to the information output 47

Firmware (multiplex channel operates under the control of channel firmware, located together with processor firmware in firmware memory (control memory). This allows you to store any control word in any 20

point in time to execute either processor or multiplex channel firmware.

Multiplex channel firmware is prioritized with respect to processor firmware. As soon as the need arises to run the channel firmware, the processor firmware

immediately start up and start 30 devices. Retrieving channel firmware from control. After they are executed, the execution of the processor firmware continues.

An input-output operation in a microprogram multiplex channel starts with a special processor command that specifies the addresses of the channel and the peripheral device and with the help of special channel control words, which are indicated either in the problem program or formed using a special control prog memory. These control layers are stored in the local memory and, if necessary, are returned to the control memory. At the same time, the possibility of simultaneous channel with several devices with the definition of control words can be stored in the control, i.e. the control volume and the number of subchannels, from the storage of control to memory memory circuits are used as many

frames (for example, an I / O supervisor), specifies the command code, the initial one control word, the address of the working memory for data exchange, the number of data bytes transferred, and other control signs that, under the control of a special channel 50 firmware A device control word is generated.

After forming the device control word, the channel frame starts organizing the volume with the peripheral device according to the standard output interval. In this case, the information byte together with the counter from the processor is transferred to the information through the information from the processor, register 62, the second information output 2 registers and register 3. The channel identifiers from

The formation of the control word of the device is performed using several cells in the local memory of the processor, built on semiconductor storage elements, whose speed is commensurate with

register memory speed, which significantly reduces the time of channel firmware operation. To this end, the control word of the device, if it is necessary to save it, is rewritten from the processor’s local memory not into the operational memory, but into the control memory, which is much faster than the operational memory. memory

Since the channel can work with several peripheral devices (subscribers) simultaneously, for each subscriber it is necessary to save

his control word. For this purpose, a special area is stored in the control memory for storing the control word for each subscriber. Moreover, the common area in the control memory is allocated so that the selection of the control words from the control memory can be organized at the address of the peripheral device with a specific base defining the beginning of the array. This makes it easy to quickly retrieve the control word for a specific peripheral from the control memory.

The control word is placed in the local memory of the processor and, if necessary, is copied back to the control memory. Thus, the possibility of simultaneous operation of a channel with several peripheral devices is determined by the number of control words that can be stored in the control memory, i.e. the amount of control memory or the number of subchannels allotted for storing control to the cich words, the local memory uses as many cells as necessary for storing

one control word,

one control word,

After forming the control word of the device, the channel firmware starts to communicate with the peripheral device (subscriber) via the standard I / O interface. At the same time, the information data byte together with the control bit from the processor is transmitted to the subscriber via information input 21 from the processor, register 62 to the second information output 26 of block 2 registers and register 3. The control channel identifiers from the processor

9. 1305693

Transmitted to the subscriber via information,: $ input 21 from processor, trigger 63, registers 62.64 and 65, information outputs 26 and 30 of block 2 re- and from the outputs of the element OR 73 and 72 through output 33 of block 6 signals and then through register 4 to control output 23 to the subscriber. Moreover, the trigger identifier from the RAB-K channel is output from the output of the flip-flop 63, register 64 from the first to quarter-H outputs — from the sample distribution identifiers from the RVK-K channel, the address from the ADR-K channel, the PREP interrupt, blocked identifiers, ka from the BLK-K channel, respectively; Setting all identifiers from

0

with transmitted. This control is performed during the channel operation when data is transferred from the processor to the subscriber,.

The operation of the equipment of the channel associated with the transfer of data from the subscriber to the processor is carried out in diagnostic mode by recording in the register 60 receiving dummy identifiers from the subscriber through the issue register 62 and the switching unit 5 with further analysis of the elements removed from the groups of elements 12 and the information output 25 to the processor known in advance of the first and second outputs of the register 65 are issued control identifiers from the UPR-K channel and information from the INF-K channel.

The information data byte together with the control bit from the subscriber to the processor comes from information input 18 from the subscriber through the group of elements I 61 and the group of elements I 10 and information output 25 to the processor. The control signals from the subscriber to the processor are received from the group control input 22 from the subscriber through the group of elements AND 68, the group of elements OR 69 into block 2 of the rHCTjioB via information input 27 and further through the subsynchronization register 59, the receive register 60, through in20

25

thirty

channel, besides the identifier of the samples from the FBR-K channel, is performed by firmware. The setting of the RAB-K identifier is also performed by the control signal when turning on the power of the processor according to the control input 19 of the power on. Setting the BBR-K signal is performed automatically when the power is turned on and turns off from the OR 73 element to the corresponding register-amplifier 4 value.

A reset of all identifiers from a channel is also performed by firmware. However, the most common identifiers UPR-K and INF-K can be reset by hardware in the process of channel operation.

, - on t 35 when communicating with the subscriber. Hardware

format output 39 of block 2regist-;

„„ - „ID reset is performed in

ditch and from the outputs of the elements IL85 and

register 65 by generating a reset signal from element 81, which the register 65 by generating a reset signal from element 81, which via 86 via information output 36 of analysis unit 7 together with the generated

Is at the output of this element

on the node Y test digit through ,,,,.

", 40 in the absence of identifiers from

a group of elements And 11 and information output 25 to the processor. Moreover, from the first, second, third, fourth, fifth, sixth and seventh outlets of ADR-A, UPR-A and INF-A, and the absence of a clock signal coming from the processor to the channel through syn, “tail 38” to the fourth input of the register 60 receptions are issued and ..

, TLAG1 l - ment and 81. typifiers of work from the subscriber RAB-A,

the address from the ADR-A subscriber; a sample from the VBR-A subscriber; the requirement from the TFB-A subscriber; disconnection from the OTK-A subscriber; control from the UPR-A subscriber; and information from the INF-A subscriber, respectively. Control of the transmitted information from the processor to the channel by the information input 21 from the processor and right; the operation of the UPR-K and INF-K associated with this pn in the channel of the hardware of the channel equipment is performed by two special-controlled, by returning this signal information - the signal A from the output of the element to the processor through groups of elements AND OR 85 and signal B from the output of element 12 and 13 and its comparison in the processor OR 86, whose combinations are analyzed

The presence or absence of identifiers from a subscriber is analyzed by firmware. However, for a quicker analysis of identifiers frequently used in the management from the RAB-A subscriber - ADR-A, INF-A, and UPR-A in combination with the presence or absence of identifiers from {ADR-K Sanal,

IDs, Setting all IDs from

0

with transmitted. This control is performed during the channel operation during data transfer from the processor to the subscriber,.

The operation of the equipment of the channel associated with the transfer of data from the subscriber to the processor is carried out in diagnostic mode by recording in the register 60 of receiving dummy identifiers from the subscriber through the issuance register 62 and the switching unit 5 with further analysis of the I 12 elements removed from the group and the information output 25 to the processor is known in advance0

five

0

channel, besides the sample identifier - from the FBR-K channel, is performed by firmware. The setting of the RAB-K identifier is also performed by the control signal when turning on the power of the processor via the control input input 19 of the power supply. Setting the BBR-K signal is performed automatically when the power is turned on and turns off from the OR 73 element to the corresponding register - amplifier 4 constant.

A reset of all identifiers from a channel is also performed by firmware. However, the most common identifiers UPR-K and INF-K can be reset by hardware in the process of channel operation.

register 65 by generating a reset signal from element I 81, which, by means of UPR-K and INF-K, two special control signals are formed in the channel — signal A from the output of the element OR 85 and signal B from the output of the element OR 86, combinations of which are analyzed

The presence or absence of identifiers from a subscriber is analyzed by firmware. However, for a quicker analysis of identifiers frequently used in the management from the RAB-A subscriber - ADR-A, INF-A, and UPR-A in combination with the presence or absence of identifiers from {ADR-K Sanal,

controlled by one microcommand in the processor, identical to the analysis of three identifiers from the subscriber RAB-A, UPR-A, INF-A, for the analysis of which three micro-commands are required.

The table shows the combinations of signals A and B.

ORAB-A installed

0INF-A installed

1UPR-A installed 1RAB-A off

In addition, if the channel has a final interrupt of the type Channel terminated, which is analyzed by firmware, the firmware in register 64 sets the sign of the interruption from the third output of register 64 through input 31 of the control signal generation unit to the first input element I 70, on

the second input of which arrives inverse-35 takes the data byte and sets

The new ID is RAB-A. Thus, the identifier BLK-K is automatically formed in the channel and is given to the subscriber in the absence of the identifier RAB-A until the final interruption is processed, i.e. until the interrupt signal is cleared by firmware.

The identifier from the subscriber TRB-A from the fourth output of the register 60 through the input 42 of the suspension enters the processor. At the end of each microcommand, the processor analyzes the presence of this signal and, if it exists, suspends

Does the implementation of processor micro- 50, etc. If the combination of signals

programs and starts executing channel firmware.

For the example in FIG. 7 shows a block diagram of the algorithm for transferring data bytes from a subscriber to a channel initiated by the subscriber.

Communication at the initiative of the subscriber begins with the subscriber issuing to the channel

five

- fO

f5

ome30 aa

1305693 -12

TRB-A identifier. This identifier from the pause input 42 enters the processor. The processor at the end of execution of each E1 micro-command analyzes the presence of the TRB-A signal, the TRB-A Signal is present, the processor suspends the execution of the processor microprograms and begins the execution of the channel ones. Thus, the input to the channel firmware is made. Further, according to the algorithm, the channel exposes the identifier of the RVB-K, the subscriber exposes his address and the identifier ADR-A, the channel, analyzing the presence of the identifier ADR-A, receives the address from the subscriber. The subscriber's address and the microprogram base form the device control word (UIC) address, after which the channel responds to the subscriber by issuing the UPR-K identifier and removing the identifier of the RVB-K identifier, which indicates to the subscriber that the subscriber’s address is received ( UPR-K) and the subscriber can continue to communicate on his own initiative (remove RTD-K). Next, the channel. reads the CCD from the control memory (UE) and writes it to the local memory (MP). At this moment, the removal of the ADR-A identifier is hardware analyzed and the UPR-K identifier is removed by hardware. Next, the channel analyzes the signals A and B. The combination of 10 of these signals, i.e. subscriber put data byte and identifier INF-A - channel

20

25

an INF-K identifier that tells the subscriber that the data byte is received by the channel. The channel then modifies the counter and the data address and writes the received data byte to the RAM. At this moment, the removal of the identifiers INF-A and RAB-A is analyzed in hardware and the identifier INF-K is removed in instrumentation. After the data byte is written to the operational memory, the channel begins to analyze the signals A and 6 of the next time. Combination 10 — the channel receives the next byte from the subscriber

AI 6 11, i.e. the subscriber clears the RAB-A identifier, which tells the channel that the subscriber stops communicating with the channel, the channel writes the control word of the device from the MP to the UE. This completes the execution of the channel firmware and the processor proceeds to continue the execution of the previously interrupted processor firmware.

The assignment in the firmware multiplex channel and the floating volume of the sub-channels; 1lov and the possibility of their arbitrary assignment are performed as follows.

Using the register 110 of the switching node 17 fixation dials n-bit code that defines the maximum number of subchannels or the maximum Hbtt amount of UE, which is allocated for storing control words of the device during the execution of a reset firmware

systems, this code, through the group e-mail, 5 of which is intended for the storage, and 111 is read into the processor via information code 25 to the processor and is stored in the UE as a characteristic of the volume of subchannels, which corresponds to the control memory for the microprogramme multi-access channel. the information is used to assign subchannels in the process of executing the next I / O command. If the subchannels are not all used, the assignment of the subchannel is accomplished. If there are no free subchannels, the I / O command is terminated. And in

In this case, the firmware of the channel is forming n consecutively addressed

It matches such a result sign that is formed by the channel in the event that when executing an I / O command it turns out that there is no necessary peripheral device. Such an algorithm for generating an indication of the result of an input command execution — in the absence of free subchannels, is selected on the basis of instructions to indicate to the user that, with the existing number of peripherals connected, the maximum number of subchannels is selected incorrectly. Such a conclusion must be made by the user when the operating system (or any other system) standardly assumes that there is no specific peripheral device, but in fact it connects to the channel and functions normally. Thus, the proposed organization of a floating number of subchannels allows the user to select the minimum number of subchannels for his own purposes and, if necessary, quickly correct it.

Arbitrary assignment of subchannels, i.e. the ability to assign any subchannel to any pepery ry.

the device with the further release of this subchannel after the end of communication with the peripheral device is executed by hardware-microprogramming using the equipment of microprogram multiplex1: channel, and, in particular, block 14 encoders, node 15 registers, node 16 decoders, two tables located in the UE, and several lill cells necessary for the operative processing of control information.

The first table contains 256 consecutively addressed UE cells, each address of the assigned subchannel for a specific peripheral device. The addressing of the cells in the first table is performed at the address of the peripheral

the device for which the I / O command is being executed. The first table, moreover, is intended for the storage of a sign, which indicates that it is assigned to this peripheral

device subchannel or not. When assigning a subchannel, this feature is established. After the end of the peripheral operation, this flag is cleared. The second table contains 5

0

five

0

five

cells for storing n-bit words (in this case, eight cells for storing 32-bit words in each cell) together with the word pointer of the second table, which consists of one eight-bit word and which is located in the cell of the local memory (Fig. 13) is used to form the address of the free subchannel. The second table defines the maximum number of subchannels that can be reserved for the firmware multiplex channel. In this case, the eight 32-bit words of the second table define the maximum number of subchannels of 256.

The eight-bit position code of the word pointer of the second table is used to quickly find a free subchannel from the total number of subchannels.

The address of the free subchannel is formed from the address of the word in the second table and the address of the bit in this word. In this case, the address of the word of the second table is determined by the bit address of the pointer of the second table, located in the cell MP1 (Fig. 13),

.-

therefore, the address of the free subchannel is formed from the address of the bit in the index of the words of the second table and the address of the bit of the corresponding word of the second table.

The sub-channel address formation for a specific peripheral device is performed as follows.

The total number of subchannels is defined by the total number of bits set to the zero state in the words of the second table. Moreover, the presence of free subchannels defined by the word of the second table is characterized by the corresponding bit of the word pointer of the second table. For example, if the third bit of the pointer of the second table is set to 1, then there are no free subchannels that are addressed by the word bit of the second table to address three. The initial setting of the minimum number of subchannels, which is determined by the code dialed on the switching register 110, is made by firmware by setting the appropriate number of bi indexes of the second table and the word bits of the second table to one.

At the beginning of the execution of the I / O command at the address of the peripheral device, which is specified in the I / O command and which is stored in the MP4 cell, the row of the first table is selected in the MP2 cell. The purpose of this sample is to determine whether a subchannel is assigned to the peripheral device addressed in the I / O command or not. The determination is made by analyzing the subchannel assignment flag. If a subchannel is assigned, therefore, the peripheral device addressed in the I / O command is busy, the I / O command is terminated. If no subchannel is assigned, therefore the peripheral device is free, the I / O command continues and the attempt to assign a free subchannel is completed. The availability of free subchannels is analyzed for this purpose. The analysis is performed by checking for the presence of zero bits in the pointer of the second table. If there are no zero bits, i.e. There are no free subchannels, the channel terminates the execution of an I / O command with a result sign characterizing how it would be from

W

J5

25

20 t 30

- the absence of a peripheral device addressed in the I / O command. If there are free subchannels, the address of the free subchannel is generated. The analysis of the availability of free subchannels and the formation of the address of the free subchannel are performed as follows.

The contents of the cell MP1, i.e. a pointer to the words of the second table, via the information input 21 from the processor, is output to the block 1 4 encoders. At the same time, the byte O arrives at the input of the priority encoder 87, byte 1 - to the input of the encoder 88, byte 2 - to the input of the encoder 89, byte 3 - to the input of the encoder 90. Each of these priority encoders at its first, second and third address outputs generates a three bit code which is the address of the first bit (starting from zero), which is in the zero state and which indicates that the word of the second table to this address has at least one free subchannel. If, for example, there is no zero bit in byte O, the priority encoder 87 excites the fourth control output, i.e. in the group of words of the second table addressed by bits of byte O of the pointer of the words of the second table, there is not a single free subchannel. The fourth outputs of the priority encoders 87-90 arrive at the first to fourth inputs of the priority encoder 94. Therefore, if there is not a single bit in the pointer of the second table indicating the presence of a free subchannel, then the control output of the priority encoder 94 is excited. then the two-digit address code received from the first and second outputs of the priority encoder 94 indicates the address of the first byte (starting from zero), in which there is at least one free subchannel, and a three-bit day th code obtained at the outputs of the multiplexers 91-93 indicates the address of the first bit in the word, which defines a free subchannel. The information from the block 14 of encoders via the information output 48 enters for the register 15 into the register 15, the line 97 stores the sign of the presence of free subchannels, the line 96 the byte address, the line 95 the address of the bit in the byte. Thus, by analyzing

35

40

45

50

The state of register 9o determines the presence of free subchannels. If there are free subchannels, the five-digit code received from registers 100 and 102 determines the address of the word in Table 2, in which there is at least one free subchannel. The indicated ana: p1z is performed by firmware by reading information from the information output 49 of the register node. Pro-jg corrects the corresponding byte.

The readable pyramid code of the elephant address of the second table is stored in the MPZ cell. At this address from the second table is read the word that is stored in the cell MP5. Then the word | 5 cell MP1, the word of the second table from the cell MP5, is output into block 14 of the cipher ML5 is written into the second

pointer to the second table by adding this byte to the constant received from the decoder 107. The corrected byte is written to

The rathors are similar to the index of the words of the second table and are further stored in the node 1-5 of the registers. After this, the firmware performs a similar analysis of information from register 99 and registers 101 and 103,

Thus, after analyzing the two layers: the pointer of the second table and one of the words of the second table, the full address of the free subchannel is obtained. This address is recorded in cell MI12, and then at the address of Table 1, Stored in Cell MP4, is copied along with the indication that the subscription is assigned to the first Table 1.

After the subchannel has been assigned, it is necessary to correct the word of the second and, if necessary, pointer of the words of the second table. For this purpose, the address code of the bit in the byte of the word of the second table and the code of the address of the bit in the byte of the pointer of the second table from registers 103 and 102 through lines 106 and 105 respectively through the information input 50 of the decoder node are fed to Е: decoder moves 108 and 107 Next The address code of the byte received from register 101 is corrected by the corresponding byte of the word of the second table, which is stored in the MP5 cell, by adding this byte with the constant obtained from the output of the decoder 108. After that, the corrected layer of the second table is checked for met the presence of free subchannels in it. For this purpose, the corrected word of the second table from the cell

The organization of a floating number of subchannels, moreover, allows for flexible and simple way to adapt to the user's conditions by providing him with the number of subchannels that are necessary only for him to create certain connotations.

P5 is fed to the information input of 21 blocks of encoders. And on the register 99 of its figuration of peripheral devices, the sign of the presence of the free organization of their parallel operation, subchannels, is memorized. This feature is being analyzed. If there are free subchannels, the word of the second table from the MPZ cell

using the minimum amount of control memory for storing subchannels.

rewritten into the second table at the address, KOTOpbttl is stored in the MPZ cell. The assignment of subchannels ends. If there are no free subchannels, it is necessary to adjust the corresponding byte of the pointer of the words of the second table located in the MP1 cell. For this sharing, the byte address code obtained from register output 100,

the cell MP1; the word of the second table from the cell ML5 is written into the second

pointer to the second table by adding this byte to the constant received from the decoder 107. The corrected byte is written to

0

0

five

P

five

0

the table. The assignment of subchannels ends,

Subchannel release is performed after the end of communication with the peripheral device when the corresponding subchannel is not needed. Subchannel release is performed by firmware.

Thus, the hardware-microprogramme method of distributing a floating number of subchannels, which allows with minimal hardware costs to efficiently assign any subchannel to any peripheral device during the execution of an I / O command, eliminates the strict dependence of the number of peripheral devices connected to the microprogram multiplex channel. the number of allocated subchannels, caused by matching the address of the peripheral device to the address subchannel, which leads to the possibility for flexible adaptation to conditions of the user in terms of connection to a channel of a wide range of peripherals in quantitative composition.

The organization of a floating number of subchannels, in addition, allows flexible and easy way to adapt to the user's conditions by providing him with the number of subchannels that are necessary only for him to create peripheral devices defined by him, and organizing their parallel operation.

figuration of peripheral devices with the organization of their parallel operation,

using the minimum amount of control memory for storing subchannels.

191305693

Claims (2)

Invention Formula one . Firmware multiplex channel on, auth.St. P 1256036, characterized in that, in order to expand the functionality by arranging a floating number of subchannels and their arbitrary distribution, 20 the processor's processor input, while the group of bit outputs of the command decryption unit is connected to the corresponding bits of the enable inputs of the register node and the enable inputs of the decoder node and subchannel fixing node, the information output of the encoder block is connected to the information input of the register node, output the input node of the decoders. 2. The channel of claim 1, wherein the subchannel latching node contains a register and. the group of encoder encryption units, the register node, the node of which is connected to the information decoders, the subchannel latch node, the information input of the encoder unit being the channel input for connecting to the information output of the processor, and the outputs of the register register register, A decoder node and a junction with the first inputs of the elements. And the latching of subchannels are connected to the group, the second inputs and outputs of which form the microprogram multiplex output, respectively, enabling. channel for connection to the information input and information output of the node. 3 20 the processor's processor input, while the group of bit outputs of the command decryption unit is connected to the corresponding bits of the enable inputs of the register node and the enable inputs of the decoder node and subchannel fixing node, the information output of the encoder block is connected to the information input of the register node, output the input node of the decoders. 2. The channel of claim 1, wherein the subchannel latching node contains a register and. The group of the electors is connected to the informational elements AND, and the outputs of the register are connected to the first inputs of the elements AND of the group, the second inputs and outputs of which form respectively permitting. input and information output node. Fia. 27 71 Rj J / FIG. 75 , 0 7 J 73 72  J3 Ш1 - J2 ".five SO U7 JOS 106 t 51 9 foxoff about nanu MUHponpoepafing J Install R5B-ME there is, La subscriber address reception Forping Ady & CcU Record the date of the day and date of the race62. l L. Zolisat UPR-N and PQ6-H ff pesucmpt) 65, BC 1 (12} one Read from the U / 1 of the CIC and. write to MP  Instrumental ana / iu- JupyefTjcft CHflmue A4R-A and equipment not removed UPR-n 2 (12) WITH Fy code eleven fa  ayt with i / tf / ifcmoHoffum about petucmfi 95 INP L Moffu9 uifu / o ffamt eve / nvuH and cffpoc Record 9annmh LOP byte o I byte 1 U Bottom a tf words table Z Country of Table 1 ADVS Tab / Gitsy Z Affpec Tob / Gitsy 1 Word Tob / 1itsh Z FIG. / J Editor I. Shulla Compiled by S. Pestmal Tehred A. Kravchuk Proofreader. Cherni Order 1453/47 Circulation 673 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 I Lpporatn o8- 1 iOH is analyzed) removal, pl I and instrumental i-type i byte 2 byte J pp ppg paragraph 5 / V / 74 PP5