SU1288927A1 - Device for measuring telegraphy rate - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to increase the reliability of measuring the speed of wiring. The device contains a selector 1 of the fronts of parcels, el-t I 2, setting g-5, main counter 6, two decoders 7 and 11, additional counter 8, (p-1) el-t I 9, (P-- 1) reversible counters 10. The serially connected el-t 3 delays and trigger 4 locks are newly introduced. 1 il. Zmd (L tc 00 00; about N3 5 (f (7) Sog Sch0 (9) 5oe m (188} Sog

Description

The invention relates to telecommunications and can be used in the regeneration and measurement of telegraph signals as an automatic wiring speed switch (automatic speed), in synchronous and start-stop communication systems at automated receiving and transmitting radio centers.

The purpose of the invention is to increase the reliability of measuring the speed of wiring.

The drawing shows the structural electrical circuit of the device for measuring the speed of wiring.

The device contains a parcel selector 1, an additional element And 2, a delay element 3, a lock trigger 4, a master oscillator 5, a main counter 6, a first decoder 7, an additional counter 8, (n-1) elements 9, (n-1) reversible counters 10, the second decoder I.

The device for measuring the speed of wiring works as follows.

The digital (telegraph) signal from the output of the demodulator (not shown) is fed to the input of the selector 1 of the fronts of the parcels, from the output of which short pulses corresponding to the moments of polarity of the parcels are fed to the first input of the additional element I 2 and through element 3 delays - to the installation input S of the trigger 4 blocking. The delay time in element 3 is equal to the duration of the pulse at its input and is 0.1-0-0 μs. The signal corresponding to the logical "1, from the output of the blocking trigger 4 is fed to the second input of the additional element I 2, opening it. The pulses from the output of the master oscillator 5 are fed to the counting input of the main counter 6, which each edge of the parcels from the output of the delay element 3 is set to the zero (initial) state. The signals from the information outputs of the corresponding bits of the main counter 6 are fed to the information inputs of the decoder 7, which allocates code numbers corresponding to the selection zones of single parcels for (n-1) the highest wiring speeds from the n values used in the communication line. The duration of the temporary main counter 6 corresponds to the duration of a single parcel, taking into account the width of the selection zone for the second lowest wiring speed. When the counting period expires from the output “Overflow of the main counter 6 pulse arrives at the input of the additional counter B and the input R of the locking trigger 4, setting the latter to the“ O ”state that locks the element 2.

The signals from the outputs of the decoder 7, corresponding to the selection zones of single parcels of the corresponding wiring speeds, are fed to the first inputs

the corresponding elements And 9, the number of which is 1 less than the number of speeds used in the communication line. The second inputs of the elements And 9 served fronts parcels

from the additional element And 2 in the time interval of the first counting period of the main counter 6. If — but the expiration of the first counting period — did not change the telegraph signal, then the additional element And 2 is locked and does not pass the next alternating sign to the inputs of the And 9 elements, which eliminates the effect crushing in pauses between soobdeni mi.

The fronts of the parcels from the outputs of the AND 9 elements arrive at the inputs of the "Addition of reversible counters 10, the number of which is equal to the number of elements AND 9, before starting operation (at the moment of switching on the device) are set to the zero state. As the fronts of parcels arrive at the corresponding reversible counters, they will increase.

The value of the code is a number. At the same time, the inputs “Subtraction of the reversible counters 10 from the corresponding 1 outputs of the additional counter 8 receive pulses with a threshold intensity, the value of which is in K times the speed of the telescoping. The value of K is advisable to take in the range of 50-100. This eliminates the effect on the measurements of crushing and marginal distortion of parcels.

As the code number increases in

the corresponding reversible counters 10 of their most significant bit will be transferred to the “1. At the same time, in their extreme positions ("0000 and" 1111 for a four-bit binary counter)

are blocked, i.e., the transition from the state "1111 to the state" 0000 and from the state "0000 to the state" 11 1 is prohibited. Signals- corresponding to the logical voltages "1 or" O, from the outputs of the higher bits of the reversible counter 10 are supplied

to the inputs of the decoder 11, which by their values determines the operating speed used in the line and controls the electronic switch (not shown) of the speed. If at the outputs of all reversible counters 10, the signals are equal to “O, then the dendrarator 11 outputs

signal "I for the lowest wiring speed.

As an example, the drawing shows the technical implementation of the depot 1 1

for 3 wiring speeds (50. 100 and 200 baud or 47, 94 and 188 baud). In this case, the counter 10--1 indicates by its state the presence or absence of a speed of 200 baud, and the counter 10-2 indicates the speed of 100 baud. If the line is operating at a speed of 200 baud, then the signal “1 at the output of the decoder 11 will be 200 baud, and at the other two outputs (100 baud and 50 baud), respectively,“ O, etc.

Claims (1)

Invention Formula A device for measuring the speed of wiring, comprising a parcel selector, a master oscillator, a main counter, the outputs of which are connected via the nerve decoder to the first inputs (p-1) of the And elements, the additional counter, the additional And element, and the second decryptor, characterized in that The purpose of increasing the measurement accuracy is a series-connected delay element and a blocking trigger, the output of which is connected to the second inputs (p-1) of the AND elements and (p-1) reversible counts via an additional AND element The outputs of which are connected to the inputs of the second decoder, while the output of the transmitter edge selector is connected to the input of the delay element and to another input of the additional element I, the output of the master oscillator is connected to the counting input of the main counter, the input “Reset of which is connected to the output of the delay element, and output "Overflow is connected to another input of the blocking trigger and to the input of an additional counter, the outputs of which are connected to the inputs" Subtraction of the corresponding reversible counters, inputs "Addition of which connected to the outputs (n-1) of the elements I, where n is the number of wiring speeds.