SU1277109A1 - Device for interrupting programs - Google Patents

Abstract

The invention relates to digital computing and is intended to implement interrupt systems in multi-machine computing systems. The purpose of the invention is to increase speed. The device contains an interrupt register, a mask register, five groups of AND elements, two OR elements, five flip-flops, an address decoder, a block of generalized interrupt signal, an output register, a priority device, an encoder, five AND elements and two delay elements. The introduction of an address decoder, an output register, a priority device, a switch, a four-way switch, four triggers, two delay elements, three AND elements and OR elements and the execution of a series of connections is new. 3 il. W

Description

The invention relates to computing and can be used to implement interrupt systems in multi-machine computing systems. The purpose of the invention is to increase the speed of the device. FIG. 1 shows a block diagram of a device for interrupting the programs of FIG. 2 is a block diagram of a generator of a generalized interrupt signal; figure 3 is a block diagram of the priority node. The device for interrupting the program contains a decoder 1, a register 2 in water, a mask register 3, a register 4 are broken, a priority node 5, a cipherto 6, a group of elements And 7, a group of elements And 8, a group of elements And 9, a group of elements And 10, element group 11, block 12, generalized interrupt signal, element OR 13, triggers 14-19, elements AND ZU-24, element OR 2b, delay elements 26 and 27, device code outputs 28, device interrupt signal inputs 29, informational device inputs 30 devices, signal input 31 Device swapping, Signal input 32, signal course 33 Device interrupt requirement, signal input 34 Providing device interrupt, device interrupt signal output 35, signal device input 36, output 37, block 12 input 38, Generalized interrupt signal generation block 12 () contains elements AND 39-43, elements NOT 44 and 45. Triggers 46 and 47, delay element 48. Priority node 5 (FIG. 3) contains triggers 49, elements And 50. The device operates as follows. Before starting, all the triggers and registers are set to O (the setup circuit in O in FIG. 1 is not shown). The device works in the following modes; Recording the mask register, Interrupt, Interrupt reception, Control 1 and Control 2. In the Mask register recording mode, the device operates as follows. At the information inputs-outputs 30 of the device, the control computer sets the register address 3 masks, resulting in the decoder output. 1 a single signal appears, which is. the leading edge of the signal at input 31, output by the control computer, is written to the trigger 15. The control computer removes the address and sets the mask code, which is recorded in register 3 by the leading edge from the output of the And 21 element, to the inputs of which the signals from the trigger output 15 and the signal from input 32, generated by the computer and the procedure for recording. In the Output Interrupt mode, the control computer sets the address of the register 2 of the output. At the first output of the decoder 1, the unit appears which is the leading edge of the signal 31, is entered into the trigger 14. The signal 32, in the case of the output register address, sends the interrupt code through the element 20 into register 2 and sets the trigger 19 into one state. The single signal of the direct trigger 19, through the element 22 (to the second input of which in this mode a single signal is fed from the inverse output of the trigger 17) opens those elements and the group of elements 7 and at first in the moves of which are supplied by single signals from the output of register 2. At the same time, a single signal from the direct output of the trigger 19 through the delay element 27 sets the trigger 19 to the zero state. Thus, at the outputs 28, there are single signals corresponding to 0; they do not have the interrupt code in register 2, and the duration of these signals is determined by the parameters of the delay element 27. In the Interrupt Reception mode, the pulse signals at the inputs 29 of the interrupt signals through the AND 9 elements (the second inputs of the AND elements present a unit from the inverse output of the trigger 17 in all modes except the 1 m Control modes Control 2) leading edge pushes the units into the corresponding register bits 4, except for those bits that are set to one in register 3. Signals from the outputs of register 4 are fed to the inputs of the OR 13 elements, and the signal that there is an interrupt from the output of the OR 13 element is fed to the input 38 of the block 12. Simultaneous signals Register 4 is fed to the corresponding inputs of the priority node.

The interrupt signal from input 38 of block 12 is fed to the first input of element 40. In the absence of a signal to Interrupt 34, trigger 46 is set to one. In the presence of a signal 34 Interrupt is provided (i.e. the control Edm reads the interrupt vector of any another device that requested an interrupt earlier), trigger 46 is set to one only after removing this signal. In this way / at the output 33 of the Signal Requirement of the device, a single signal appears that goes to the corresponding control computer. In response, the control computer exposes a read signal and a signal 34 Providing the interrupt, the leading edge of which is unguarded.

interrupts from the 4th interrupt register output are written to the corresponding triggers 49 of node 5. This record is made to avoid changing information at the output of node 5 during the interrupt vector procedure if a higher priority level arrives. Signal 34 Providing interrupt when a 33 signal is present Interrupt request sets in one state, trigger 47, the signal from whose inverse output supplied to the input of element And 43, prevents further propagation of the signal. Providing interrupt to the output d 35. At the same time, signal 34 The provision of interruption sets a trigger 46 in O and the device removes the signal 33 Interrupt Requirement. If

interrupt device

programs do not expose signal 33, the interrupt request (i.e., this) signal was set by another, lower priority device), the signal Termination request through delay element 48 and AND element 43 goes to output 35. Delay element 48 is entered to prevent short-time signal 35 with signal availability 33 Interrupt request. If there is one at the direct output of the trigger 47 (i.e. the presence of a signal 34 Provision of a fault in response to the signal 33 An interrupt request) and the presence of a single signal at the input 36. Of the signal Read

A single signal appears at the output 37 of the block 12; it is fed to the second inputs of the elements M I -, the outputs of which are connected to the corresponding bits of the informational ion outputs-outputs 30 of the device (in the proposed device, the main trunk structure, t. e. a structure allowing unification of like inputs-outputs with the help of mounting OR). The first inputs of the And 1 i elements are fed from the output of the encoder 6, the inputs of the rotor: 1L gats of the node 5, the time delay between the arrival of the signal 34 Provision of interruption and the appearance of a single si: rk, la.p. entry 37 of block 12 ensures the end of the transition process at node 5 and encoder 6 that

information on the device outputs 30 and thus prevents the reception of incorrect information of the control computer. At the same time, the signal from output 37 of block 12 is fed to the second inputs of elements AND 10, the first inputs of which are connected to the corresponding outputs of node 5. Since by this time there is only one code at the outputs of the node, which is in a single composition corresponding to the interrupt vector output, At the outputs of elements 10, there appears only one unit sign, which sets the corresponding register register 4 to the zero state. The presence of one in the corresponding trigger 49 of node 5 will not affect the further operation, since In the new service cycle of the device for interrupting program 1, it will be reset by the signal 34 Interrupt Provision.

A trigger 47 is set to but it provides the immutability of the left state being positive1; the front of the signal AND 42. which is formed; at removal of a signal 36 Reading. When the signal is removed, the Reading also closes the And 11 elements and stops outputting the interrupt vector to the device 30 outputs, after which the control computer removes the signal 34 Providing the interrupt and most allows the device to set (if there are unserved requests for interruption in the 4 interrupt register) ) next signal 33 request 512 The Monitoring mode starts with the reference of the control computer at the mask register address of a higher priority device than the controlled one (if it exists). In this case, in the mask register, all units are entered, Then the control computer records at the address corresponding to the excitation of the third (in the Control 1 mode) or the fourth (in the Control 2 mode) output of the decoder 1 of the monitored device address. In this case, the trigger 16 is set to one. A positive edge of the signal from the output of the trigger 16 sets the trigger 17 to one, and in the Control 1 mode, the trigger 18. In the Control 2 mode, the trigger 18 is set to the Zero state. The signal from the direct output of the trigger 17 through the delay element 26 sets the trigger 17 to the zero state after the time required to perform the control operations. The control computer then performs a write operation to register 2, while the zero signal from the inverse output of the trigger 17 prohibits the interrupt signals 29 from entering the register D and through the And 22 element prohibiting the passage of the interrupt signals to the outputs 28. As after writing the interrupt code In the output 2 register, a single signal appears on the forward edge of the flip-flop 19, in the Control 1 mode, through the AND 23 element, the second inputs of the And 8 elements are given the enable signals, and in the Control 2 mode, the enabling signals are sent to the And 8 elements through the elements m AND 24. Thus, at the inputs of register 4, interrupt signals appear in accordance with the interruption code in register 2 and in accordance with the control 1 mode or the control, 2. Further operation of the device is similar, in the mode, interrupt reception . The control computer accepts the interrupt vector and, if the computer is working in the Control mode, compares the received interrupt vector with the output information (mask register 3 code, output register 2 code, Control 1 or 2), then writes a new state (defined by the program) in 9 of the heads of the masks of higher priority devices than the controlled ones, and returns to the execution of the interrupted program. B. In case, if the computer did not go into Control 1 or Control, then the control computer proceeds to execute the program set by the interrupt wind. Formula of the Invention A device for interrupting programs containing an interrupt register, a mask register, five groups of AND elements, the first OR element, two AND elements, two triggers and a generating unit for a generalized interrupt signal, the group of informational inputs of the mask register connected to the device information input group , the outputs of the elements And the first group are connected to the zero inputs of the corresponding bits of the interrupt register, the outputs of the elements And the second group are connected to the code outputs of the device, the clock input of the first three The gamer is connected to the signal exchange device input, the generating unit for the generalized interrupt signal contains the first element AND, the first element NOT and the first trigger, characterized in that in order to improve speed, a decoder, an output register, a priority node, an encoder, four triggers, two delay elements, three AND elements and a second OR element, the information output outputs of the device being connected to the inputs of the decoder, the output register and the outputs of the AND elements of the third group, the first and second outputs of the decoder are connected with the information inputs of the first and second triggers, respectively, the third output of the decoder is connected to the first output of the first OR element and the information input of the third trigger, the fourth output of the decoder is connected to the second input of the first OR element, the output of which is connected to the information input of the fourth trigger, clock inputs of the second and the fourth flip-flops are connected to the signal input of the device exchange; the direct outputs of the first and second flip-flops are connected ::; with the first inputs of the first and second elements And, respectively, the second inputs of which are connected to the signal input device recording, the direct output of the fourth trigger is connected to the third input of the third trigger and the clock input of the fifth trigger, the fourth output of the third trigger and the fourth element And with the input of the first delay element, the output of which is connected to the zero input of the fifth trigger, the output of the first element And is connected to the clock input of the output register and to the single input of the sixth an igger, the output of which is connected to the second inputs of the third and fourth elements I, to the first input of the fifth element I and to the input of the second delay element, the output of which is connected to the zero input of the sixth trigger, the inverse output of the fifth trigger And and with the first inputs of elements AND of the third group, the second inputs of which are connected to the inputs of the interrupt signals of the device, the output of the fifth element AND connected to the first inputs of elements AND of the second group, the outputs of the output register are connected to the first inputs elements of the first group, with the second inputs of the elements of the second group, the direct and inverse outputs of the third trigger are connected to the third inputs of the third and fourth elements AND, respectively, the output of the third element I is connected to the second inputs from the first to n / 2th (h- the number of requests for elements I and the first, the output of the fourth element I, and connected to the second inputs from (h / 2 + 1) -th through the h elements of the AND group of the first group, the output of the second element I connected to the clock input of the mask register, information inputs of the mask register with element outputs and h of the fourth group, the outputs of the mask register are connected to the zero inputs of the interrupt register, the outputs of elements AND of the third group are combined with the outputs of the same elements of the And fifth group and connected to the clock inputs of the register of interrupts, the outputs of the register of interruptions are connected to the input group of the priority node and the second element OR, node outputs

priority connected to the group of inputs of the encoder and with the first inputs of elements And group 11, the outputs of the encoder connected with the first inputs of elements AND of the fourth group, the second inputs of which are connected to the second inputs of the same elements And fifth group, the generation unit of the generalized interrupt signal further comprises the second, third, fourth and

0 fifth elements, the second element fIF, the second trigger and the delay element; moreover, in the generating unit of the generalized interrupt signal, the output of the first element I is connected to the single input of the first trigger, the zero input of which is connected to the input of the first element NO, with the first inputs of the second and third And elements and through the delay element with the first input

0 of the fourth And element, the second input of which is connected to the zero output of the second trigger, the zero input of which is connected to the output of the third And element, the output of the second element is NOT

5 is connected to the second input of the third element I, the output of the first element is NOT connected to the first input of the first element I, the output of the second element I is connected to the single input of the second trigger, the direct output of which is connected to the first input of the fifth element I and the second input connected with the input of the second element NOT, the second input of the second element I, is connected to the output of the first trigger and is the output of the interrupt request of the device, the input of the interruption of which is connected to the input of the first element of the HE block general the interrupt signal and the clock input of the priority node, the output of the fifth element AND of the generator of the generalized interrupt signal is connected to the second inputs

5 elements of the fourth and fifth groups, the output of the second element OR is connected to the second input of the first element AND the generation unit of the generalized interrupt signal, the input signal Read device is connected to the input of the second element NOT of the generation unit of the generalized interrupt signal, the output of the fourth element And which is the output interrupt the device.

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Claims (1)

Invention Formula A device for interrupting programs containing the interrupt register, mask register, five groups of AND elements, the first OR element, two AND elements, two triggers, and a generic interrupt signal generation unit, the group of information inputs of the mask register connected to the device information input group, outputs the elements of the first group are connected to the zero inputs of the corresponding bits of the interrupt register, the outputs of the elements of the second group are connected to the code outputs of the device, the clock input of the first trigger is connected to input home signal exchange device, the generation unit of the generalized interrupt signal contains the first element AND, the first element NOT and the first trigger, characterized in that in order to increase speed, a decoder, an output register, a priority node, an encoder, four triggers, two delay elements are entered into it , the three elements And the second element OR, and the information inputs and outputs of the device are connected to the inputs of the decoder, the output register and the outputs of the elements of the third group, the first and second outputs of the decoder are connected to the information the inputs of the first and second triggers, respectively, the third output of the decoder is connected to the first output of the first OR element and to the information input of the third trigger, the fourth output of the decoder is connected to the second input of the first OR element, the output of which is connected to the information input of the fourth trigger, clock inputs of the second and fourth triggers connected to the signal input of the device exchange; direct outputs of the first and second flip-flops are connected ::; with the first inputs of the first and second elements And, respectively, the second inputs of which are connected to the signal input device recording, the direct output of the fourth trigger is connected to the third input of the third trigger and the clock input of the fifth trigger, the fourth output of the third trigger and the fourth element And with the input of the first delay element, the output of which is connected to the zero input of the fifth trigger, the output of the first element And is connected to the clock input of the output register and to the single input of the sixth an igger, the output of which is connected to the second inputs of the third and fourth elements I, to the first input of the fifth element I and to the input of the second delay element, the output of which is connected to the zero input of the sixth trigger, the inverse output of the fifth trigger And and with the first inputs of elements AND of the third group, the second inputs of which are connected to the inputs of the interrupt signals of the device, the output of the fifth element AND connected to the first inputs of elements AND of the second group, the outputs of the output register are connected to the first inputs elements of the first group, with the second inputs of the elements of the second group, the direct and inverse outputs of the third trigger are connected to the third inputs of the third and fourth elements AND, respectively, the output of the third element I is connected to the second inputs from the first to n / 2th (h- the number of requests for the elements I and the first, the output of the fourth element I, and connected to the second inputs from (h / 2 + 1) -th through the h elements of the AND group of the first group, the output of the second element I connected to the clock input of the mask register - En with outputs of elements And of the fourth group, the outputs of the mask register are connected to the zero inputs of the interrupt register, the outputs of elements AND of the third group are combined with the outputs of the same elements of the And fifth group and are connected to the clock inputs of the register of interruptions, the outputs of the register of interruptions are connected to the input and output group of the priority node and the second element OR the node outputs 0 five 0 five 0 five 0 five priority connected to the group of inputs of the encoder and with the first inputs of elements And group 11, the outputs of the encoder connected with the first inputs of elements AND of the fourth group, the second inputs of which are connected to the second inputs of the same elements And p - that group, the generating unit of the generalized interrupt signal additionally contains the second , the third, fourth and fifth elements, the second element fIF, the second trigger and the delay element; moreover, in the generating unit of the generalized interrupt signal, the output of the first element I is connected to the single input the first trigger, the zero input of which is connected to the input of the first element NOT, to the first inputs of the second and third elements I and through the delay element to the first input of the fourth element I, the second input of which is connected to the zero output of the second trigger, the zero input of which is connected to the output of the third element And, the output of the second element is NOT connected to the second input of the third element And, the output of the first element is NOT connected to the first input of the first element And, the output of the second element And is connected to the single input of the second trigger, direct output which is connected to the first input of the fifth element AND, the second input of which is connected to the input of the second element NOT, the second input of the second element AND is connected to the output of the first trigger and is the output of the interrupt demand of the device, the input providing the interruption of which is connected to the input of the first element NOT generating a generalized interrupt signal and with a clock input of the priority node, the output of the fifth element And the generating unit of the generalized interrupt signal is connected to the second inputs of the elements of the fourth and fifth groups, the output Here, the second element OR is connected to the second input of the first element AND the generation unit of the generalized interrupt signal, the input signal of the device is connected to the input of the second element NOT of the general generation interrupt signal generation unit, the output of the fourth element I of which is the output interrupt device. / w w R J6 .t Rkdaktor E. Kopcha Compiled by M. Kudr seam Tehred I.Popovich Proofreader E.Roshko Order 6667/42 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 FIG.