SU1262701A1 - Generator of pseudorandom binary sequence - Google Patents

Abstract

The invention relates to computing. Its use in systems with complex discrete-coded signals allows for improved reliability of operation. The pseudo-random binary sequence generator contains four triggers, an OR element, two AND elements, and a switch. The introduction of two more OR elements, in the case of a failure in the formation of a Barker sequence, provides for a return to normal operation in one clock cycle. I silt, 2 tab. (ABOUT

Description

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; The invention relates to computing and can be used in systems with complex discrete-coded signals.

The purpose of the invention is to increase functional reliability. I The drawing shows a functional diagram of a pseudo-random binary sequence generator.

The pseudo-random binary sequence generator contains the first 1, second 2, third 3 and fourth 4 triggers, first 5, second 6 and third 7 elements OR, first 8 and second 9 elements AND and switch 10, the first and second inputs of which are connected to logical buses 1 and about.

The pseudo-random binary sequence generator works as follows.

In the case that when the switch 10 is connected to the logical bus O, the outputs of the elements 8 and 9 turn out to be in the state O, regardless of what potentials are present at their other inputs. Since the outputs of the elements AND 8 and 9 are connected to the inputs of the elements OR 6 and 7, the same potentials appear at the output of the last with each clock pulse as on the direct outputs of the flip-flops 1 and 3. The flip-flops 2-4 at the same time work as the shift register, and the trigger 1, both of whose inputs are connected to the forward output of the trigger 4, operates in the counting mode. In this case, the entire device is a generator of the M-sequence of significance N 15.

The state of the direct outputs of the flip-flops 1-4, varying with the clock frequency, is presented in tal.1.

Table

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The states of the M-sequence generator periodically (with a period of 15 cycles) are repeated.

In the case where switch 10 is connected to the logical 1 bus, if we take the status of the forward outputs of the flip-flops 1 - 4 - 11.11 to the initial one, the first eleven cycles (from zero to ten) the device operates as an M-sequence generator in accordance with the table .one. Upon the arrival of the eleventh clock pulse, a state of the direct outputs of the 000 flip-flops is established.

Since the inverse outputs of the flip-flops 1 - 3 are at the same time in state 1II, the output of element AND 9 appears 1, which through the element OR 6 enters the direct input of the second trigger 2. Consequently, with the next clock pulse, the direct output of the second trigger 2 is set to 1, not O, as in the case of generating an M-sequence.

Claims (1)

Thus, following state 0001, 1100 follows, and since the inputs of the And 8 element are connected to the direct outputs of the flip-flops 1 and 2 and the reverse outputs of the flip-flops 3 and 4, the output of the And 8 elements appears 1, which through the OR 7 element comes to the direct input of the fourth trigger 4. On the front of the next tactical impulse 1, it is rewritten to its direct output, and after 1100, 1111 occurs, after which the cycle of the device repeats. Table 2 presents the states of the generator, which in this case forms the Barker sequence at the output of the OR 5 element. The main cycle of states presented in Table 2 contains thirteen vertices and corresponds to the value of the Barker sequence. Three s. STATES, namely GOOD, 014 1000,, lie outside the main loop. Consider the behavior of the device if it accidentally turns out to be in one of them. Detectors made on AND 8 and 9 are tuned to a combination of the direct output states of the 1100 and 000 X flip-flops, respectively, where the crawl X denotes the indifferent state of the trigger 4. In this state, 0000 triggers 1-4 cause the the output element And 9 logical 1, which through the element ISH-1 6 post-falls to the input of the second trigger 2 and with the next clock pulse is transmitted to its output. Thus, state 0000 is followed by state 0100, which lies in the main loop (Table 2). Therefore, the AND 8 element not only implements the 0001-1 100 transition, which is necessary to form the Barker sequence, but at the same time serves to eliminate the device zero cycle. The other two states, 1000, are not detected outside the cycle by elements AND 8 and 9. Therefore, if the device is in one of them, then transitions 1000 will follow. VET, 1110-1111 in accordance with Table. I, as in the case of generating the M-sequence. Thus, in the event of a malfunction, the device returns to normal operation in one cycle. Claims A pseudo-random binary sequence generator containing four flip-flops, the first and second AND elements, the first OR element, the output of which is the device output, and the switch, the first input of which is connected to the logical 1 source bus, all synchronization inputs. the triggers are combined, the forward outputs of the first and second triggers are connected to the first and second inputs of the first element, And the inverse outputs of the first, second and third triggers are connected to the first, second, and third inputs of the second element, in order to increase functional reliability, it introduced the second and third elements OR, the outputs of which are connected with the installation inputs in 1, respectively, of the second and fourth triggers, the direct outputs of the first and third triggers are connected to the first inputs of the second and third OR elements, respectively, the second input of the third OR element is combined with the first input of the first OR element, and connected to the output of the first AND element, the third input which is combined with the third input of the second element I and the installation input of the fourth trigger on O, the direct output of which is connected to the installation inputs of the first trigger and the second input of the first element I.PI, inverse you move fourth trigger 627016 connected to the direct input of the first element And, the fifth input of which is combined with the fourth input of the second element And and connected to the output of the switch, the second input of which is connected to the bus of the source of logical O, the trigger synchronization inputs are connected to the device synchronization input, the output of the second element I 10 is connected to the second input of the second element OR, the inverse output of the first trigger is connected to the input of the installation O of the second trigger, the direct and inverse outputs of which are connected to 15 inputs of the installation, respectively in I and in O of the third trigger.