SU1262480A1 - Dividing device - Google Patents

Abstract

The invention relates to computing and is intended for use in digital arithmetic devices. The aim of the invention is to simplify the device. The device contains a register of the dividend, the register of the divider, the register of the result, the blocks of forming the additional code and the node generating 11 the approximate reciprocal of the divider, containing the block of the permanent memory, the block of the multiples, the sum of the multiples and the adder with the spread of the transfer. The result of the calculations is formed in three iterations. 3 il.

Description

Yu

about

ts9

nU

00 I1 The invention relates to computing and is intended for use in digital arithmetic devices. The aim of the invention is to simplify the device. Figure 1 shows the functional scheme of the device for dividing; in fig. 2 - j-th split interval of the representation of the divisor; in fig. 3 - structure of the register divider The device contains a register of 1 dividend, a register 2 of a divider, a register 3 of the result, blocks 4–8 multiplication, blocks 9 and 10 of the extension of the additional code, block 11 of fixed memory, block 12 of formation of multiples, block 13 of summation multiples and the sum of the torus 14 with the distribution of the transfer. Blocks 11-13 and adder 14 form a node 15 generating an approximate value of the reciprocal of the divider. Block 12 contains 16 multiplier shapers. The basis of the operation of the node 15 of generating an approximate value of the reciprocal of the divider is the method of piece-linear approximation. The range of representations of the n-bit divider is divided into 2 equal intervals, where i is the number of most significant digits of the divider, beginning at its 2nd to i-th, containing the number of the interval in which the divider falls. The most significant bit of the divider (first) is not considered, since its value is always 1. D and D, are the values of the divider, J & T is the limiting j-interval, and i / Dj and 1 / Dj are the corresponding function values Y 1 / X. The approximated value of the function n, corresponding to a certain value of the divider D lying in a given interval, is determined by the formula Atgci,. –5U D - D; DJ- D ,, 1 Substitute (2) into (1), we get where & I - L. Tgd values All intervals can be calculated in advance and placed in the permanent memory. The value of D is hardware represented by the higher bits of the register divider. The value of L can be represented by an additional code of the digit of the divider, starting with (i +) - ro and ending with the nth, or approximately the opposite code of these bits. The number of bits of tg ot and & can be reduced to some values that provide such an accuracy of the calculation of Y, which is sufficient for its further use in the division device. Therefore, truncated tgo values are placed in the fixed memory cells, and are replaced by the value a, for which the inverse outputs of the group of bits of the register of the divider are used, namely, with (i + l) -ro by Kth. Then the expression (3) takes the form .. 1 (D ,, + D). The truncated tgd values placed in the permanent memory are pre-converted in such a way that each pair of bits of the initial value corresponds to a pair of bits of the converted value. At the same time, the possible combinations of a pair of bits of the converted value correspond to the following values of multiple values (D: + &) Oh -,. 00-- O 01- (+1) 10- (+2) 11- (-1). Due to this, signals that are lower than the output of the permanent memory can be fed to the control inputs.

shapers multiple without additional transformations.

Each (16 times multiplier from block 12, under the influence of -pairs of signals arriving at its control input-od, sends to the output a direct (+1) shifted one bit to the left (+2) or an inverted (-1) value the code arriving at its informational inputs, or blocks the transmission (0).

The device works as follows.

Registers 1 and 2 are recorded as divisible and divisor, respectively. Seven bits of the divider from the 2nd to the 8th are sent to the address input of the block 11 of the permanent memory. At the output of block II of the permanent memory, an 18-bit code appears, which is fed to the control input 17 of block 12. Next, each pair of bits of this code is fed to the control input of the corresponding shaper.

The bits from the 1st to the 8th register 2 are fed to the first information input 18, block 12 and further to the first information inputs of all 16 multiples of drivers.

The inverse outputs of the group of bits from the 9th to the 19th register 2 are connected to the second information input 19 of block 12 and further to the second information inputs of all drivers 16 times.

The codes arriving at information inputs 18 and 19 of block 12, together form the code, whose multiples are formed by 16 times shapers under the influence of signals from the output of block 11 of the permanent memory and the incoming to their control inputs.

The generated multiples are summed in the additional code on the block. 13, from the output of which the two-code code is fed to the inputs of the adder 14 with the spread of hyphenation. At the output 20 of the adder 14 with the propagation of transfers, an approximate value of the reciprocal of the divider Ud is formed.

In the first iteration in block 4, the multiplication of the dividend N is performed and in parallel in block 5 - the divider D

on yq. As a result, a new value of the dividend N1 and a new value of the divider D1 are formed, which contains 14 identical bits - zeroes or ones to the right of the binary point.

In the second iteration, in block 9 of the formation of the additional code from the 29 most significant bits of D1, an additional code is generated by which N1 and D1 are multiplied in blocks 6 and 7, as a result of which new values of N2 and D2 are formed. At the same time, after the first discharge, D2 will contain 28 identical bits.

In the third iteration in block 10, an additional code is generated from D2, by which r block 8 is multiplied by N2, and the result of multiplication — the quotient is written into the result register 3.

Claims (1)

Invention Formula A device for dividing, containing the registers of the dividend, the divider and the result, two blocks of forming an additional code, five multiplication blocks, a block of permanent memory, the inputs of the first group of the first and second multiplication blocks are connected to the outputs of the bits of the dividend and divider registers, respectively the outputs are connected respectively to the inputs of the first group of the third multiplication unit and the first unit to form an additional code, the outputs of which are connected to the inputs of the first group of the fourth multiplication unit, the outputs of the third b the multiplication loop is connected to the inputs of the first group of the fifth multiplication unit, the outputs of which are connected to the inputs of the result register bits, and the inputs of the second group are connected to the outputs of the second additional code generation unit whose inputs are connected to the outputs of the fourth multiplication unit, the inputs of the second group of which are connected to the inputs of the second group of the third multiplication unit and the outputs of the first block of formation of the additional code; the inputs of the fixed memory unit are connected to the outputs of the bits of the first group of the register divider I differ. This is because, in order to simplify the device, it contains a unit for forming multiples, a unit for combining multiples and an adder with propagation of transfer, the information inputs of the unit for forming multiples are connected to the direct outputs of the first group of bits And for inverse outputs of the second groups of divider register bits, control inputs of the formation block multiples are connected to the outputs of the fixed memory block, and outputs are connected to the inputs of the summation block 806 or multiples, the outputs of which are connected to the inputs of the adder HAND transfer bits whose outputs are connected to second inputs of the second and first blocks umnogruppy married. Cf) U8t -x For informational bmdy (pop Multipliers and multiple address memory bmd SflOKO On the other hand informational 0X0y formers multiple Fig.Z