SU1259506A1 - Start-stop reception device - Google Patents

Abstract

The invention of computer technology. The reliability of the device is increased by providing automatic test control. The device contains an input matching unit (BCB) I, cyclic trigger 2, frequency shaping block 3, frequency divider 4, two elements AND 5 and 6, starting trigger 7, element OR 8, a serial-parallel converter (SPT) 9, tact generator 10, information source imitation unit (BII) 11 and AND-OR element 12. When working with a real information source, the input start-stop information passes through the AND-OR element 12 of the BSC 1. In the imitation mode of the external information source formed in biii 1 by signal m of the digital computer. At the end of the imitation of the callback of the code message, the start-stop information is received in the device. The goal is achieved by introducing BIII II and the element AND-OR 12. The device also differs in the implementation of RFP 9 and BSHP P, illustrations of the implementation are given. 2 hp f-ly, 3 ill.

Description

The invention relates to computing and can be used in telegraph data transmission equipment.

The purpose of the invention is to increase the reliability of the device by providing automatic test control.

FIG. Figure 1 shows the structural electrical circuit of the proposed device; in fig. 2 is a series-parallel converter circuit; embodiment; in fig. 3 is a block diagram of an information source simulation, an embodiment.

The start-stop receiver contains (Fig. 1) an input matching unit 1, a cyclic trigger 2, a frequency shaping unit 3, a divider 4 frequencies, first and second elements AND 5 and 6, a starting trigger 7, element OR 8, a series-parallel converter 9, shaper 10 clocks, block P imitation of the source of information, the element I-IZH 12. Serial-parallel converter 9 (Fig, 2) contains the element AND NOT 13, the counter 1A of transmission pulses, the first and second decoders 15 and IS, the counter 17 of the word length blo

18 rollover modulo, register

19 reception, the first element AND 20, the first element OR 21, the buffer register 22 characters, the second element AND 23, the second element I.PI 24.

The imitation source information block (FIG. 3) contains a decoder 25, a counter 26 of the number of code parcels, a register 27, an AND-NO element 28, an HE element 29, a trigger 30,

Start-stop receiver device operates as follows.

To provide software and hardware health monitoring of the start-stop receiver, a specific command and control signal (FIG. 1) is generated from a digital computing map (PCM) (not shown), using which the imitation mode of the external information source is set by block 11, and in register 27 (Fig. 3, a simulated eight-bit of the code dressing is recorded. In contrast to working with a real source of information, when start-stop information passes through the second input of the I-1SH 12 element of single matching

block 1, in the simulation mode, the input start-stop information is formed by the block 1, which simulates the information information simulation, which operates as follows. in a way. After receiving the spgnal, trigger 30 (Fig. 3) with the trailing edge of the control pulse switches to the opposite state, as a result of which the register {operation 27 of the register 27 changes, from the parallel recording mode it switches to the sequential shift mode. The recorded code message will begin to shift in the register with the wiring frequency.

Due to the presence in the register 27 of the feedback from the low-order to the high, in this mode the transmission of identical code messages corresponding to the recorded transfer mode is simulated.

The number of code messages in the start-stop channel for each message, for example, is fixed, therefore the source simulation block 11

5 of the information contains a counter 26 of the number of code messages with a decoder 25, which is set to a fixed message length. At the end of the imitation of the simulated message

0, at the output of the decoder 23, a signal is generated which, through the IS-NE element 28, blocks the shift circuit of the register 27. The IS-NE element 28 is controlled by the signal from the output of the HE element 29. Thus, the simulation of the transmission of the code message is ended.

Reception start-stop information is as follows.

Before receiving the telegraph message, the cyclic trigger 2 is in an idle state and the signal from its output prevents the operation of the 4 frequency divider and does not pass the signal from the output of the AND-OR element 12 through the second element 6 to the serial-parallel converter 9. To allow passage through The AND-OR 2 element of information from the input matching unit 1, before receiving from the communication device, sends a signal to the first control input. The input receive channel is in the state corresponding to the level of the Stop signal, and is constantly polled by the oscillator frequency (not shown) 9 arriving at the cyclic trigger trigger sync input 2. The transmission cycle of each code message always starts from the token 5

0

five

0

five

Start signal, which, unlike the Stop signal, has the opposite logic level. Upon receipt from the output of the element AND-OR 12 transition from Stop to Start, i.e. when it appears on the (informational input of a cycle trigger 2 level corresponding to the start signal), the first frequency pulse of the generator coming from the formation unit 3 is often sent to the cycle trigger trigger 2, the latter is set to the operating state and the signal from its output enables the 4 frequency divider and passing through the second element 6 of the input signal to the information input of the buffer register of the sign 22 (FIG. 2) of the series-parallel converter 9. From the output of the divider 4 frequencies in a time slightly higher than its half of the transmission period of a single bit produces a signal which, arriving at the first input of the first element of the IZ, polls the signal at the output of the IH-IH element 12 at the zero state of the starting trigger 7. During this time, the transition signal of the noise will disappear and, if the line still maintains the level corresponding to the Start signal, the start bit arrives, otherwise, at the output of the first element I 5, a false start protection signal, which, having passed through OR 8, will reset the cyclic trigger 2 and divider 4 to its initial state. frequencies. In the case of the Start signal reception, the prohibit signal from a false start will not pass through the first element and 5 and the 4 frequency divider continues counting, as a result of which the second output of the divider 4 frequencies opens the Strobe signal, which, on the trailing edge, sets the start trigger to one. 7. Thus, in the word length counter 17, the first signal Reset will not pass and the code send bit corresponding to the Start signal will not be written to the buffer register.

If the operating frequency of the divider 4 frequency is inversely proportional to the duration of the transmission of one bit of information, then the Strobe signal from its output is generated at the wiring frequency. So the sample coming from the output of the second element And 6

j y "h 20 25 Q

five

five

five

at the information input of the buffer register 22 characters, the code message is sequentially written to it using gate signals received at the single input of the buffer register 22 characters from the output of the first element OR 21. At the same time, the gate signals are counted in the word length counter I7 in order to block the reception of marker signal Stop. After the reception of the information part (sign) of the first code parcel at the output of the second decoder 16, the signal of 5 T is output, with the formation of which the transmission pulse counter 14 is reset. In addition, the signal 5 T from the output of the second element IL 24 permits the passage of frequency through the second element I 23 into the counter 14 transmission pulses. Using the counter 14 of the transmission pulses of the first decoder 15, the output of the second element And 23 forms a bundle of five pulses, which is fed into the shift circuits of the buffer register 22 characters and the reception register 19. In addition, this batch of pulses from the output of the second element AND 23 passes through the element OR 8 and sets the cyclic trigger 2, the starting trigger 7 and the divider 4 frequencies to the initial state. Since the output of the buffer register 22 characters is connected to the information input of the reception register 19, the received character advances on it. At the end of the transmission at the output of the first decoder 15, a signal that will block the transmission of pulses through the second element 23 is received. The reception of the following ix code orders occurs in the same way as described. With the arrival of the following start signal, the cyclic trigger 2 will once again be set to one state and the next character will be received, and the information through the shaper 10 clocks will be advanced to the output.

At the end of the reception of the last character (in the example given, the third) at the output of the second decoder 16, a signal that, having passed through the NAND 13 element, will turn on the shaper of 10 cycles. The latter works as follows. When the second element NAND 23 is closed, i.e. at its output potential corresponding

the level of logical t, the shaper of 10 clocks operates in the parallel i mode at its first time, Porlet, as at its input 2

When the signal 5 is corresponding to the logical O, it goes into the sequential shift mode. The I recorded in it will begin to sequentially shift from the beginning to the end. A series of signals is formed at the output of the imaging unit 10, one of which records the control code from block 18 to the check bits of receive register 19, another signals the pre signaling in the digital computer on the device output, and the word 17 is reset to the initial state. Thus, the start / stop receiving device is ready to receive and pack the following telegraph message code messages.

Claims (3)

1. Start-up receiving device containing a series-parallel converter, an input matching unit and a series-connected frequency shaping unit, a frequency divider, to the second input of which the output of the cyclic trigger is connected, the first element I, whose second input is connected to the first i- fy the input of the second element, the OR element, to the second input of which the first output of the series-parallel converter and the start trigger are connected, the outputs of which are connected to the third input of the first element AND, whose second input is connected to. the first input of the cycle trigger, and the first input of the series-parallel converter, the second input of which is connected to the second input of the starting trigger and the second output of the frequency divider, the third and second inputs of which are connected respectively to the output of the OR element and the second input of the second element AND, the output which is connected to the third input of the series-parallel converter, the quarter input of which is connected to the second input of the cycle trigger, to the third input of which the output of the I-PI element is connected, and the output of the frequency generator, the second output of which is connected to the first input of the input Jq 15 20 25 five -jo d, 0 five the matching unit, the second input of which is the information input of the device, and the first input of the clock generator, the first and second outputs of which are connected respectively to the fifth and sixth inputs of the series-parallel converter, the second output of which is connected to the second input of the clock generator, the third output of which The control output of the device, the information output of which is the third output of the series-parallel converter, characterized in that, in order to increase over helix devices by providing an automatic test control, the sequentially connected information source simulation block and the AND-OR element, the second and third inputs of which are connected respectively to the output of the input matching unit and the first input of the information source simulation block, are entered into it connected, respectively, the fourth output of the series-parallel converter and the third output of the frequency shaping unit, with the first control input of the device in a fourth input of AND-OR, the output of which is connected to the first input of the flip-flop cyclic, and the first, fifth and chetvertsh inputs information source simulation unit are respectively the second control, and the mounting kodo- BSiM inputs. 2, the device under item 1,. This is due to the fact that the series-parallel converter contains the first element AND, the first OR element, to the second input of which the output of the second element AND is connected, the sign buffer register, the receive register and the convolution unit are connected to the second input. module. the output of which is connected to the second input of the reception register, the third input of which is connected to the first input of the transmission pulse counter, the output of which through the first decoder is connected to the first input of the NAND element and the output of the second element AND, the first and second the moves of which are connected according to. with the output of the first decoder and the output of the second element: a, OR, the first input of which is connected with the second input element AND-NOT and the first output of the second decoder, the input and the second outputs of which are connected respectively to the output of the word length counter, the first input of which is connected to the output of the first element AND, and the second input of the second element, OR, the output of which is connected to the second input the transmission pulse counter, wherein the first and second inputs of the first element AND, the second input of the buffer register of the sign, the third input of the second element AND, the second input of the word length counter and the fourth input of the reception register are respectively The eighth, second, third, fourth, fifth and sixth inputs of the series-parallel converter, the first, second, third and fourth outputs of which are, respectively, the output of the second element AND, the output of the element AND-NOT, the second output of the receive register and the first output of the second decoder . 3. The device according to claim 1, characterized in that the simulator of the source of information contains a counter of the number of code messages whose outputs are connected to the inputs of the decoder, the output of which is connected to the first input of the I-NB element, the output of which is connected to the first input of the register, and the first input of the trigger, the second input and output of which are connected respectively to the input of the element 0 NOT, the output of which is connected to the second input of the I-NB element, on the second input of the register, the output of which is connected to the third input of the register, the fourth input of which is connected 5 with the first input of the counter of the number of code messages, the third input of the trigger, the second input of the counter of the number of code messages, the second input of the trigger, the fifth input of the register and the first input of the counter of the number of code messages are respectively the first, second, third, fourth and fifth the inputs of the information source simulation block whose output is the output. regist roo Compiled by B. Nosov. Editor L. Gratilo Tehred I. Popovich Order 5141/59 Circulation 624 Subscription VNIIPI USSR State Committee for inventions and discoveries I3035, Moskva, Raushsk iab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 tfka.3 Proofreader G. Reshetnik