SU1249488A1 - Automatic system for testing and diagnostic checking of digital units - Google Patents

Abstract

The invention relates to automation and computing and can be used for functional and diagnostic control of digital nodes and blocks. The task of automated monitoring and diagnostics in the management of a system from controlling computing facilities having various interfaces is solved. The task is solved by inputting into the system containing the test driver (FT), the programmable power supply unit of the control object (BLOCK), the strobe pulse generator (VIF), the operator panel (SW) and the control object (OK) connected to the internal system backbone. , a programmable interface unit (PBS), the inputs of which are connected to the computer, and the outputs to the internal trunk of the system. The CBE is configured to include bus drivers, data registers and addresses, address and command decoders, a clock multiplexer, a microinstructor memory (MI), and a microprogram control unit (BMU), which allows programming the joint operation of the system with control computing facilities. For example, with a computer, with different interfaces. In this case, the computer controls the system and processes the results of the monitoring, the BSS connects the computer with FT, BFC, PSF, software. In the process of monitoring and diagnostics, FT provides control tests and removes feedback from OK; The software indicates to the operator the state of the system and transfers control actions from the operator to the computer; The BMU, together with the PM and the multiplexer, analyzes the control signals from the computer and, through the data register and bus drivers, sets information signals, and through the address register - address signals to the system's internal backbone. The principle of microprogram control of the interface with a computer implemented in this way makes it possible to use the system with various control computing means. 1 hp f-ly, 11 ill. i (L

Description

The invention relates to automation and computing and can be used for functional and diagnostic control of digital nodes and blocks.

The purpose of the invention is to expand the scope of the system, which will allow it to be used in conjunction with a computer, as well as with equipment in the KOP standard.

FIG. Figure 1 shows a block diagram of an automated monitoring and diagnostic system (ASKID) with a programmable interface; - FIG. 2 is a schematic diagram of a programmable interface; in fig. 3 is a block diagram of a strobe pulse former; in fig. 4 is a block diagram of the operator’s console; in fig. 5- functional diagram of the test driver; in fig. 6 is a block diagram of a firmware control unit (EMU); in fig. 7 is a block diagram of the work algorithm (BMU) when the system is connected to a computer; in fig. 8-11 is a block diagram of the algorithm of the BMU operation when the system is connected to the CPC channel.

The system contains inputs 1, which are used to connect the computer, programmable interface 2, test generator 3, programmable power supply unit 4 of the control object, pulse gateway 5, operator panel 6, control object 7, system internal trunk 8.

The programmable interface node 2 contains the first information inputs 9, input 10, control information inputs 11, address inputs 12, bus driver 13, data register 14, bus driver 15, clock pulse generator (GTI), block 17. memory of microinstructions, microprogram control unit 18, multiplexer 19, address decoder 20, register 45 s; either to unidirectional inputs 9,

21 addresses, a decoder of 22 commands, informational 23, control 24 and address 25 outputs.

The outlets 23–25, together with the internal strobe-gate, the terminal supplied to the input of the object 7, then from the lines S, S1 and S2, form the internal trunk 8 of the system.

The strobe pulse shaping unit 5 includes pulse shaper units 26, 27, 28, and 30 and a time interval register 29.

The operator panel 6 contains the control register 31, the display register 32.

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impulse or potential, set the type of controlled point - the input or output of the object.

Register 36 determines the type of input test object being fed to each output: pulsed or potential. Register 37 temporarily stores the input test object. Register 38 is defined 33 controls, display elements 34.

Shaper 3 consists of address decoder 35, signal type registers - pulse or potential 36, input test 37, input-output 38, read test 39, and also from switch 40 of the buffer register 41 of the input test, AND-NOT elements 42,

outputs (inputs or moves) 43

control object, tire former 44.

Block 18 (Fig. 8) consists of the register 45 command code, register 46

checkboxes, logic circuit 47 for determining the next microcommand address, register 48 for the microcommand address, output buffers 49, lines 50 for the microcommand address, synchronization line 51,

command lines 52, control lines 53, feature entry lines 54, flag selection lines 55.

Lines 52, 53 and 55 are connected to the corresponding outlets PM 17.

The input of line 54 is connected to the output of multiplexer 19 and is used to feed into the register 46 signals the branch conditions of the exchange algorithm. Diagram 47 depending on the registers 45 and 46 and

lines 53 generates the next microcommand address, which enters register 48 and then through buffer 49 to the address inputs of memory block 17. Block 18 is clocked from generator 16 through

line 51 sync.

The system works as follows.

A computer connected to the inputs controls the system and processes the control results. The node 2 connects the computer with the driver 3, block 4, driver 5 and panel 6. Depending on the type of computer, it can be connected either to bi-directional inputs 10.

Shaper 3 allows you to submit tests and remove responses from object 7, control the type of signal

impulse or potential, set the type of controlled point - the input or output of the object.

Register 36 determines the type of input test object being fed to each output: pulsed or potential. Register 37 temporarily stores the input test object. Register 38 oprede3

, lt type of each output object: input or output. Register 39 sl 7kit for storing the test read from the object. The switch 40, depending on the state of the registers 38 and 36, supplies the input test from register 41 or from the control line to the output of the object or not. The remaining control signals arriving at the imaging unit 3 perform the following functions: S1 serves to feed the input test object by writing it from register 37 to register 41.52 to store the control object to the test sent to its inputs in register 39.

Shaper 3 works as follows.

From the register 21 through the address inputs 25 the binary code of the address is fed to the input of the decoder 35. The data from the register 14 through the driver 15, the outputs 23 and the driver 44 are fed to the inputs of registers 36-38. When the system is self-monitoring, data from registers 36-38 through the elements AND-NO 42, the imaging unit 44 and through the node 2 enter the computer. Similarly, the control object stored in register 39 is entered into the computer in the computer. The AND-NOT selects the registers and elements 35 in the presence of a control signal from the driver 5 and in the presence of the corresponding address. Thus, the computers in the registers 36-38 record the necessary data. Block 4 is turned on and off from the computer through an internal register. Panel 6 is used to indicate the state of the system to the operator, as well as to transfer control actions to the computer.

The algorithm of operation of the unit 18 when connecting the system to the Electronics-60 computer is shown in FIG. 7

The signal from the address decoder 20 through the multiplexer 19 is fed to the input of block 18. With the presence of this signal, block 18 proceeds to check for the presence of the synchronization signal of the SLEEP arriving at block 18 in the same way. If there is a BIA signal, then under control of block 18, the lower-order address bits are written from input 12 to register 21 (the number of register bits 21 is determined by the number of system registers). Then block 18 analyzes the output signal coming in through inputs 11 and multiplexer 19 from

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COMPUTER. If the output signal is passive, the input signal is analyzed. -The absence of the latter indicates an error in the operation of the node 2. 5 One computer word will require two

cycles of data exchange on the outputs 23. When transferring data from a computer (the presence of an active signal Output). Block 18 analyzes the Byte signal arriving at its input. If the signal is active, the data through inputs 10 and the driver 13 under the control of block 18 will be written into register 14. Then, depending on the parity or oddness of the address from register 21 (analysis is performed by block 18), the corresponding register of the system through driver 15 and outputs 23 the low byte or the most significant byte from register 14 will be written. Block 18 through inputs 11 will set a CIP signal indicating the computer that the data has been received and is waiting for the output signal to be output. In response to the removal of this signal, block 18 will remove the CIP signal and expect the CI signal to be removed. Disconnection of the BIA signal will indicate the end. data output on the computer.

If the Byte signal is passive, the data from the computer will also be recorded in register 30 14, but their transfer to the system registers will occur in two cycles. First, the low byte will be written to the address transmitted by the computer to register 21, and then by the signal from block 18 the address will be increased by 35 and the high byte from register 14 will be written to the new address.

If the Input signal is active, then data is output from the system to the computer. Under control of block 18, the register of the system register with the address recorded in register 21, through inputs 23 and shaper 15, is written into the lower eight bits of register 14. Then the address in register 21 with a signal 45 from block 18 will increase by one and the contents of the next register The systems will be written in the same way in the upper eight bits of the register 14.

50 The data from the register 14 through the imaging unit 13 and the inputs 10 under the control of the unit 18, which received the CIP signal, is fed into the computer. In response, the computer will remove the input signal by analyzing the block 18.

This algorithm is used to exchange data between the computer and any of the system registers.

The algorithm of operation of unit 18 when connecting the system to the CPC channel is shown in FIG. 8-11.

The following interface functions are implemented: source, receiver, device clearing, device startup, ycTpoiicTBa polling, as well as source synchronization (subroutines C and D, Fig. 8) and receiver synchronization (subroutines A and B, Fig. 8).

The operation algorithm in conjunction with the CPC can be divided into three parts: initial analysis (Fig.9), operation in the source addressing state (Fig.10), operation in the receiver addressing status (Fig.11).

In FIGS. 8-11, the logical O and logical 1 denote the passivity and activity of a cooTBTCTByraitq; ix signal

In accordance with the specified computer exchange algorithm, controlling the operation of the CPC through node 2, polls the state of panel 6, turns on block 4, loads the value of the time interval T into the driver 5 and the data into the registers of the driver Zo After filing the interface message from the computer via the CPC Starting driver 5 fails gates S, SI, 52%., Reads the responses to the test submitted to the object 7, analyzes them and indicates on the panel 6 the validity or unsuitability of the object 7 The diagnostics of the control object faults can be logged or stored In the computer memory, this process of monitoring and diagnostics of the given C1-1 -free object node 7 ends

The proposed automated system for monitoring and diagnostics of digital nodes can be used together with a computer or as an autonomous unit in conjunction with equipment

the KOP standard by programming the memory of micro-commands3 or one; it is the first; this saves the cost of creating an ASKID based on a specific computer due to its constant hardware,

Formula of invention

Claims (1)

1, Automated system for monitoring and diagnostics of digital nodes containing test generator, programmable power supply unit of the object control, strobe pulse shaper, operator panel, internal system bus, the test driver, programmable power supply unit of the control object, strobe pulse shaper, and operator panel are interconnected by means of an internal system bus, characterized in that the system, a programmable interface node is entered into it, the information, control and address inputs of which are connected to the internal backbone of the system, and the address, filling, first and second e inf ormatsionnye inputs are inputs of the system homonymous 2, Pop-up system 1, characterized in that the programmable gateway comprises first and second bus drivers, a data register and an address register, a microprogram control unit, a micro-instruction memory block, a clock generator, a multiplexer, a command decoder and an address decoder, the first to the fourth outputs of the micro-command memory block are connected to the clock inputs of the second bus driver, data register, first bus driver and address register, respectively, the fifth and sixth outputs of the block pa These micro-commands are connected respectively to the control input of the multiplexer and the second control input of the microprogram control unit, the first control input of which is connected to the output of the multiplexer, and the output to the address input of the microcommand memory block, the synchronous input of the microprogram control block is connected to the clock generator output pulses, the first and second information inputs of the multiplexer are connected respectively to the outputs of the command decoder and address decoder, the unidirectional outputs of the busbars x formers are combined with each other and are connected to the data input of the data register data inputs of the bus drivers between combined, zu and a decoder with the input commands and are connected to the output of the instruction register, the first information unit inputs are connected to the inputs and informa- unidirectional tsionnpu the outputs of the bus driver, the second information inputs of the node are connected to the bidirectional output of the first bus driver, the control inputs of the unit are connected to the seventh output of the memory module and the third information input of the multiplexer, the address inputs of the node are connected to the combined ones the inputs of the address decoder and the address register, the information outputs of the node are connected to the bidirectional output of the second bus driver, the control of the output of the node is connected to the seventh one. the output of the microinstructions memory block, and the address outputs of the node are connected to the output of the address register. lg Thebes 1 iDaiZ but . S2 Fig.Z cps ASL Phases. four LSAMK / JAMKSO Exit B 49 RAMK 48 7 5f 4/4 LVF55 VP5 LU53 LK52 Phage. 6 6 Subprogram A , I LP-G 6 LoIapro Ranma B Padprogramma C Fig By S  D at I 1MKOP-RGA and ..li (B