SU1238098A1 - Polyfunctional module - Google Patents

Abstract

The invention relates to the field of computer technology and may find application in the construction of specialized and universal computers. The aim of the invention is to reduce the number of external leads. To this end, a multifunctional module, in addition to two D-triggers, two multiplexers, element And. And triggers of zero and first bits, additionally contains two multiplexers and element And, connecting them to the rest of the circuit's nodes allows to divide all arithmetic logic operations into two groups. In the first of these, the result of operations in some kind of discharge is formed by the outcome of the specified operation code and the values of the operands in this order, taking into account the translations into it to the right and left. In the second group, the result of the operation in some discharge is deformed without taking into account transfers in this category. 2 ip., 1 tab. (L

Description

The invention relates to computing and can be used in the construction of specialized and universal computers.

The purpose of the invention is to reduce the number of external leads.

FIG. 1 shows the scheme of the proposed module; in fig. 2 - time diagrams of his work.

The multifunctional module contains triggers of zero I and first 2 bits, asynchronous drives. 3 and 4 data, first 5 and second 6 multiplexers, inputs 7 and 8 of data, synchronous data outputs 9 and 10 of zero and first bits, respectively, a group of control inputs 11 module, first 12 and second 13 D-flip-flops, module transfer input 14, module transfer code 15, first element 16 of the module 17 controlling transfer processing of the module, clock input 18 mode

l, the third 19 and the fourth 20 multiplexers, the second element And 21, the input 22 of the shift to the right of the module.

Multifunction module works as follows.

All arithmetic logic operations can be divided into two groups. In the first of them, the result of the operation and some discharge form the outcome from the specified opcode and operand values in this bit, taking into account the translations to the right and left. In the second group, the result of the operation is formed in some discharge without taking into account transfers in this discharge.

In the proposed module, for calculating the transfers and the results of almost all operations, the same multiplexers 5 and 6, controlled by the operation code arriving, are used for the group of control INPUTS 11. In this case, the arithmetic logic operations of the first group are implemented in two cycles of computer time. , in the first of which, the transfer value from each bit is calculated, which is remembered in the corresponding D-triggers 12 and 13, and in the second, the operation value in this bit, taking into account the transfer.

The binary control code supplied by the group of control inputs 11, whose width is equal to 8 bits, determines the type of operation that is implemented in a given time scale. Separation

machine time cycles per calculation cycles of transfers and results of the operation is carried out by the signal at the input 17 of the transfer processing control. If there is a logical signal at the input 17. The transfer signals for each bit are calculated. These signals are calculated by multiplexers 5 and 6 in accordance with the operation code on the group of control inputs 11, the signals at the data inputs 7 and 8, the signals from the outputs of the zero and 1 triggers of the two bits, as well as the signals at the transfer input 14 or from the output of the D-flip-flop 12. In this cycle, the D-flip-flops 12 and 13 are opened by a signal from input 17 and the value of the corresponding transfer signals is memorized. In this case, the signal from input 17 using the element AND 16 on the inverse input blocks the synchronization signal at the inputs of the triggers zero 1 and the first 2 bits. As a result, their state remains unchanged during this cycle.

When proceeding to the next cycle of tool time (TaKty of calculating the result of the operation), the signal at the input

17 transfer control

must take the value equal to the logical O. This ensures the locking of the B-flip-flops 12 and 13, which store the transfer signals, and the transmission of the synchronization pulses from the clock. The module’s input 18 to the synchronization inputs of triggers 1 and 2. In this computer time cycle, multiplexers 5 and 6 compute the result of the operation specified by the code on the control group P. P. The result of the operation in each bit is the output element (the final function three arguments: the signal at the inputs (7 or 8) of the data, the output signal of the corresponding trigger (1 or 2) and the transfer signal coming from the transfer input 14 or D-flip-flop 12. At the same time, the signal from the D-flip-flop output 13 goes to output 15 and is involved in rez formation At the time interval equal to the switching time of multiplexers 5 and 6, the result of the operation in the corresponding bits is set at their outputs and fed to the first information inputs of the multiplexers 19 and 20, respectively.

The multiplexers 19 and 20 are controlled by the output signal of the element 21, which is configured to decode the shift operation code to the group of control inputs 11. Therefore, when all other operations are carried out, the output signal of the element 21 is equal to logical 0, which in this case ensures the arrival

the output of multiplexers I9 and 20 of the information received at their first information input. Thus, the result of the performed operation in the corresponding bits is set at the information inputs of the triggers zero 1 and first 2 bits and the corresponding asynchronous outputs. 3 and 4 data. On the front of the clock to them. the pulse coming from input 18 through the open element AND 16 to the input of the synchronization of triggers 1 and 2, this result is recorded into triggers - zero 1 and first 2 bits and its formation on synchronous output buses 9 and 10 of data.

When implementing the operations of the second group, the signal at the input 17 is always equal to a logical zero and in each computer time clock (similarly indicated) the results of the operations specified by the code on the group of control inputs 11 are formed. The operations of the second group also include the right shift operation, which is implemented in the proposed device other than all other operations. When calculating the result of a shift operation to the right, unlike other operations, multiplexers 5 and 6 are not used. Upon receipt of an operation code. Shifting to the right by a group of control inputs 11, an element 21 is triggered, the output of which switches multiplexers 19 and 20. As a result , a forward right-shifting circuit is formed in which the output of each previous most significant bit is directly (via open multiplexers 19 and 20 at the second inputs) connected to the information input of the next least significant bit. On the clock edge, the result of the right shift operation is written to triggers 1 and 2 and set at the synchronous data outputs. With the serial connection of several microprocessor modules

ten

thirty

15: 20-25

five

0

five

0

five

to form a multi-bit calculator, the output 9 of each subsequent module must be connected to the input 22 of the previous module, to form a common transfer chain to the right.

The truth table describing the operation of the multifunctional module in the modes of generating transfer signals and calculating the results of the operation with all information and control inputs shows that the operation control code, received through the group of control inputs I1, to the information inputs of multiplexers 5 and 6 in the signal generation modes transfer and execution of basic operations, uniquely coincides with the values of the corresponding switching functions on the corresponding sets of arguments. From this it is obvious that, by determining the values of these switching functions on all the sets in accordance with the operation required for the implementation, it is easy to determine the control code on the input group II necessary to perform this operation. The operation control codes shown in the table are derived from the assumption that the first control input of multiplexers 5 and 6 has a weight of 2, the second is 2, and the third is 2, and the symbol A indicates the status of the flip-flops 1 and 2 of the zero and first digits and B is the number at inputs 7 and 8.

As the control code for the shift operation, any unused code or the code of any verification operation (e.g., operation) can be used. In the second case, these operations differ in the value of the signal on the control bus 17. The verification operations are performed at a single value of the signal at input 17, and the right-shift operation is performed at a zero value of this signal. In order to trigger an element 21 and when the right shift operation code is tapped onto a group of control inputs 11, it must be pre-configured to assign this code. For this, the inputs of the And 21 element, to which the zero values of the logical signals are received when there is a right-shift operation code on the group of inputs 11, should be inverse (not shown).

Claims (1)

Invention Formula A multifunctional module containing triggers of zero and first bits, the first and second D-triggers, the first and second multiplexers, the first element I, and the information groups of the inputs of the first and second multiplexers are connected to the group of inputs of the operation code of the module, the first control inputs of the first and the second multiplexers are connected to the corresponding data inputs of the module, the second control inputs of the first and second multiplexers are connected to the outputs of the zero and first time trigger of the rows and the synchronous outputs of the 55 the zero and first bits of the module, respectively, the information inputs of the first and second D-flip-flops 50 connected to the outputs of the first and second multiplexers respectively, the third control input of the first multiplexer is connected to the transfer input of the module, the third control input of the second multiplexer is connected to the output of the first D-flip-flop, the control input of the processing of the transfer of the module is connected to the synchronization inputs of the first and second D- flip-flops and inverse input of the first element I, direct input of the first element I connected to the clock input of the module, output of the first element I connected to the inputs of synchronization of the zero and first trigger th bits, the output of the second D-triggora connected to the output of modulation transfer data inputs of flip-flops zeroth and first bits are connected to asinhronnESh the data outputs of the module, the outputs of the zero and first bit triggers are connected to the synchronous data outputs of the module, characterized in that it contains the third and fourth multiplexers, the second And element, and the group of inputs of the second And element is reduced to the group of inputs of the operation code of the module, the output of the second element I is connected to the control inputs of the third and fourth multiplexers, the first the information inputs of the third and fourth multiplexers are connected to the outputs of the first and second multiplexers, respectively; the outputs of the third and fourth multiplexers are connected to information inputs, respectively, zero and first bit triggers, the second information input of the third multiplexer is connected to the first bit trigger output, and the second information output - the input of the fourth multiplexer. connected to the module in the course of the shift to the right, TaHmoStK and (lu / gs ( Compiled by V. Minakov Editor S. Lisin Tehred N. Bonkalo Proofreader A. Obruchar Order 3294 / 5G Circulation 67. Subscription VNISHI USSR State Committee. for inventions and discoveries P3035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhorop, st. GTooektnl Phie. 2