SU1231494A2 - Device for generating test sequences - Google Patents

Abstract

The invention relates to the field of computing and can be used to monitor and diagnose logic blocks as a generator of test sequences. The aim of the invention is to expand the functionality of the device by generating cyclic test sequences from bits. To achieve the goal, the device containing two registers, a comparison circuit, a counter, a generator, a trigger, an OR element and five AND elements, a second comparison scheme, a second trigger, two counters and a sixth I element are introduced. The device allows to generate cyclic for any K test sequences of 2 bits containing all possible combinations of zeros and ones in any To a number of located bits. Invention additional to auth. St. No. 1138799. 2 Il. § (/}

Description

The invention relates to computing technology and can be used to monitor and diagnose logic blocks as a generator of test sequences.

The purpose of the invention is to expand the functionality of the device by generating cyclic

g, k (test sequences from /

bits

FIG. I .based a block diagram of the device; Fig, 2 is a temporary diagram of the operation of the device,

B the device enters the clock pulse generator I s first. . counter 2, shift register 3, first comparison circuit 4, trigger 5, first 6, second 7, third 8, fourth 9 and fifth fifth AND elements, OR 11J element accumulative register 12, initial input 13, start input 14 , informational output 15 of the device, the second 16 and the third 17 counters, the second comparison circuit 18, the sixth element And 19, the second trigger

20 and a control input 21 of the device ,, the device allows to generate

for any K, cyclic test sequences of 2 bits, containing all possible combinations of zeros and ones in any: To a number of arranged bits (code rings of type A), as well as cyclic test sequences of 2 bits, containing half (2) different combinations of zeros and ones in K bits (code rings of type B),

The device works as follows

The mode of operation of the device is set by the signal from the input

21 of the state of the trigger 20. In the zero state of the trigger 20, the operation of the device does not differ at all from the operation of the known device, since in this case the additional circuits introduced and the connections do not affect the state of the circuits of the known device.

after setting the initial state of the counter 2 and register 3 supplied to input 13, and after applying / entering input 14 of the Start signal on the second,

;} the first, fourth, and third outputs of generator 1 are formed respectively. signals 22–25 (FIG. 2) synchronizing the operation of the device, signal 22 is fed to the shift input

10 register 3 and counting inputs of counters 16 and 17. With this signal, register 3 is cyclically shifted by one bit (the direction of the shift does not matter, but must remain unchanged over the entire device operation time) and the counters 16 and 17 are added to the contents the value supplied to their information input from the single and zero, respectively

20 outputs of one of the bits of the register 13, i.e. at Sinal 22, counter 16 performs unit counting: in one of the bits. Dov register 3, and the counter 17-counting zeros in the same category de. Whitefish

25 and 23 enters the control inputs of the comparison circuits 4 and 18. According to this signal on the diagram 4 of the comparison. The state of counter 2. and register 3 and comparison circuit 18 compares 30 states of counters 16 and 17. If the value of counter 16 is less than the value of counter 7., a signal 26 appears at the output of comparison circuit 18. If the contents of counter 2 contain more. the second register 3, the output of the comparison of the comparison circuit 4 is the signal 27, If the contents of counter 2 are equal to the contents of register 3, the output of the comparison circuit comparison

4p .4 signal 28 appears. The zero state of trigger 5 using AND elements 9 and 10 blocks the shift of register 12 and writing to it by signals 22 and 23 respectively, the absence of signals 27 and 28 at outputs 4, 4 comparisons using edemen - Commands And 7 and B blocks the count of counter 2 and write to register 3 by signals 24 and 25, respectively. At the same time, the input 13 of the initial state of the counting 50 is absent signals on the outputs of the element M and f -iT -n l-ie-r OOL t. "I., ... Tirm

Chip 2 and Register 3 and after the input signal 14 is applied to the Start signal, accumulator register 12 will form a type-A code ring.

The receive mode on register 12 of the type B code ring is set by setting the signal from input 21 to the one-state trigger 20. When

And 6 (signal 29) and the element OR 1 (signal 30).

The occurrence of signal 27 entails the emergence of signal 30, fed to the second inputs of elements 7 and 8. After arriving at their first inputs from generator 1, respectively, signals 24 and 25, the outputs

after setting the initial state of the counter 2 and register 3 supplied to input 13, and after applying / entering input 14 of the Start signal on the second,

the first, fourth and third outputs of the generator 1 are formed respectively. signals 22–25 (FIG. 2) synchronizing the operation of the device, signal 22 is fed to the shift input

register 3 and the counting inputs of counters 16 and 17. With this signal, a cyclic shift of register 3 occurs by one bit (the direction of the shift does not matter, but must remain unchanged throughout the device operation time) and the value added to the contents of counters 16 and 17 arriving at their information input from a single and a zero, respectively

outputs of one of the bits of register 13, i.e. at Sinal 22, counter 16 performs unit counting: in one of the bits. Dov register 3, and the counter 17-counting zeros in the same category de. The signal 23 is supplied to the control inputs of the comparison circuits 4 and 18. According to this signal on the diagram 4 of the comparison. proceeded; It compares the states of the counter 2. and the register 3 and in the comparison circuit 18 of the states of the counters 16 and 17. If the value of the counter 16 is less than the value of the counter 7. A signal 26 appears at the output of the comparison circuit 18. 3, the output of the comparison of circuit 4 of the comparison is signal 27, If the contents of counter 2 are equal to the contents of register 3, the output of the comparison of the comparison circuit

.4 signal 28 appears. The zero state of trigger 5 using AND elements 9 and 10 blocks the shift of register 12 and writing to it using signals 22 and 23, respectively. There are no signals 27 and 28 at outputs 4 comparisons using edements Both 7 and B blocks the count of counter 2 and write to register 3 by signals 24 and 25, respectively. In this case, there are no t signals on the outputs of the element M and f -iT -n l-ie-r OOL T. "i., ... Tirm

And 6 (signal 29) and the element OR 1 (signal 30).

The occurrence of signal 27 entails the appearance of signal 30 supplied to the second inputs of elements 7 and 8. After arriving at their first inputs from generator 1, respectively, signals 24 and 25, the outputs

31231

Of these elements, signals 31 and 32 appear, respectively. The signal 31, the input to the account of the counter 2, an increase in counter 2 by one. On signal 52, j arriving at the input of the permit. records in the register 3 and the reset inputs of the counters 16 and 17, the contents of the counter 10 2 arriving at its information input are written to the register 3 and the counters 16 and 17 are reset to zero. The process of shifting the register 3, cf. the states of counter 2 and register 3 in comparison circuit 4 and the values of counters 16 and 17 in comparison circuit 18 t5 and when signal 27 appears, increasing counter 2, recording its changed state in register 3 and resetting counters 16 and 17 continues until the output of the comparison of the scheme-2о we 4 of the comparison of the signal 28.

When a signal appears 28, the order of further operations performed depends on the presence of a signal 26 at the output of the comparison circuit 18. The absence of 25 signal 26 (and, consequently, the absence of signal 33 at the output of element 19) indicates that the state of the bits of register 3 must be included in the code ring of type B formed on register 12 (when forming rings The type A state at the output of the comparison circuit influences the appearance of the signal 33, since, due to the zero connection j, the trigger signal GO 33 cannot appear). In this case, the signal 28, the trigger 5 is set to a single state, and a 34, 40 signal arriving at the second inputs of the AND 9 and 50 elements appears at its single output. After the first inputs of these elements arrive from the generator 1, respectively, the signals 22 and 23, 45 signals 35 and 36 respectively appear on their outputs. Signal 35, which arrives at the input of the shift register-12, shifts register 12 by one bit. Signal 36, which enters the input of the write section 50 in register 12, writes to the place of the extreme shifted register bit 12 on the right (in the case of registers shifts 3 and 12 to the left) or at the extreme 55 on the left (in the case of shifts to the right) times the register 3 arriving at the info-. register input 1 2, Shift re 4944

the horn 12 and writing to it occurs in parallel with the shift of the register 3 and the comparison of the states of the counter 2 and the register 3 in the comparison circuit 4 until the output 28 repeatedly fails to receive the signal 28, in which the register 5 is reset.

If signal 28 is present, signal 26 indicates that the state of the bits of register 3 cannot be included in the type B code ring. Therefore, a signal 33 appears at the output of the AND 19 element, which triggers the trigger 5 Each reset of the trigger 5 after the occurrence of the signal on the signal 28 entails the appearance at the outputs of the elements AND 6, OR 11, AND 7 and AND 8, respectively, signals 29.30, 31 and 32, leading to a change in the contents of counter 2 and register 3 and reset the counters 16 and 17.

The code ring becomes ready for use after making H records in register 12, where H is the number of its bits. The code ring is formed completely after the implementation of 2 (for rings type A) or (for rings type B) entries in the register 12 ...

As a result of the device operation with Jk-5 and the initial state of counter 2 and register 3 equal to 00100; the following code ring will be generated: type 110101 lO l 1 1 1 10000010001 1 containing all 32 possible combinations of zeros and ones in five bits.

For the same initial data, the following code ring B 0011101011011111 will be generated, containing 16 different combinations of zeros and ones in five bits. The remaining 16 different combinations are contained in the code ring, obtained from the above by replacing the ones with zeros and vice versa.

1100010100100000.

Claims (1)

Invention Formula Device for generating test sequences by author. St. No. 11 38799, characterized in that, in order to extend the functionality by generating cyclic test sequences from 2 K-1 bits, the second and third counters are entered into the device, the second comparison circuit, the sixth And element and the second trigger, the single and zero outputs of the first bit of the shift register are connected respectively to the information inputs of the second and third counters, the counting inputs of which are connected to the second the output of the clock pulse generator, the reset inputs of the second and third counters are connected to the output of the third element and the outputs of the second and third counters are connected respectively to the first and second information P to the secondary inputs of the second comparison circuit, the comparison input of which is connected to the first output of the clock generator, the comparison output of the second comparison circuit is connected to the first input of the sixth element AND, the second and third inputs of which are connected respectively to the forward output of the second trigger , the output of the sixth element AND is connected to the zero input of the first trigger, the single input of the second trigger is an input of the device mode. 0W ". | With Jgshmshlj shells l jinnrmjL Jinj  ..ri JlГ1 Л .-Jto-.jrl .. 2i; rL nP LPrL .. nPIT JU. 25 26 5l.-jl 33. 3. 35-3P Tl Jl.l JL.Jl fpl4Z.Z