SU1205148A1 - Device for failure-resistance checking of programs - Google Patents

Abstract

The invention relates to digital computing and can be used to test the resiliency of a digital computer program having hardware tools and software protection against failures, organized by dividing programs into controlled areas, allowing re-execution after a failure. The device simulates a signal failure when the contents of the address register of the command of the digital computer coincide with the address of the labeled command. The signal simulation period is set by the timer. The change of the address of the labeled command is carried out automatically with a pre-set simulation step in each simulation period. The device contains a register, comparison schemes, a timer, AND, OR, triggers, an address modification block. g. W

Description

The invention relates to digital computing and can be used to test the resiliency of digital computer programs, having hardware control tools and software protection against failures, organized by dividing the programs into controlled areas, allowing re-execution after a failure.

The purpose of the invention is to expand the field of application of the device by making it possible to check cyclic programs.

FIG. 1 shows a block diagram of a device for testing programs for failure resistance; in fig. -2 - the same block address modification; in FIG. 3 - timer.

The device contains a group of elements AND 1, element AND 2, comparison circuit 3, block 4 address modifications, element OR 5, triggers 6 and 7, timer 8, comparison circuit 9, register 10, address inputs P, -, where. And - the width of the address of the digital computer, the first group of inputs 12 (- 12 c of the input, the second group of inputs 13, - 1 of the 3 entrances, input 1A of the start and the output 1 of the device. Additionally, the digital computer 16 with the register 17 of the command address and the input 18 information.

The address modification block 4 (Fig. Contains a register 19, a group of elements AND 20, a group of elements OR 21, an adder 22, a delay element 23 with taps, inputs 24 (- 24f, entries, start input 25, discharge outputs 26, - 26p, exit 27 end of work.

The timer (Fig. 3) contains a register 28 with triggers 29, local zero input 30 and local inputs 31 - 31, entries, comparison circuit 32, consisting of element OR 33, groups of elements AND 34, groups of elements OR 35, groups elements 36 and element 37, differentiation circuits 38, potential equivalence output 39, equivalence pulse output 40, a time counter 41 containing a pulse generator 42 and a counter 43, as,. This generator 42 of the pulses contains the element And 44, the element NOT 45, the element 46 delay, start input 47, the counter 43 of the time contains a group

0

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five

0

five

48

flip-flops 48, the group of elements AND 49, except for this, the timer contains the element OR 50 and a zero input 51.

A device for testing fault tolerance programs (FIG. L) operates as follows.

In the initial state, the triggers 6 and 7 are reset. The zero level from the direct trigger code 7 closes the elements AND 1 and the element AND 2, and also blocks the operation of the timer 8. The initial address is And nat. the program being tested for fault tolerance is entered by inputs 12, 12 into the address calculation block, and the final one, which is selected as the address of the first command beyond the limits of the Atsd program, at the inputs of register 10. With the inverse output, trigger 6. a single level is present at the second input of the element And 2. The adjustment of timer 8 is performed depending on the ratio of the start-up period of the program or the start-up period of the input information simulator T and the time interval between two failures on the same controlled section T at which the software fail protection does not classify them as a failure. If the timer is set to issue signals through T Tj, after it starts, if it is, then the timer is set to receive signals through T T after it starts. The input of the entry of the corresponding constant code into the timer 8 in FIG. 1 not shown. The code of the initial address from the bit outputs of block 4 is fed to the second inputs of circuits 3 and 9 of the comparison.

The launch of the device is accomplished by applying a signal to the launch input 14 of the device. This signal translates trigger 7 into one state. The unit level from the direct output of trigger 7 of the terminal triggers a timer 8, enters the third input of the AND 2 element and the second inputs of the AND 1 elements, permitting the passage of the potential command address code from the bit outputs of the register 17 of the command address of the DVR 16 to the first inputs of the comparison circuit 3 In the case of coincidence of the codes on the first and second inputs of the comparison circuit 3, the latter outputs a signal that passes through the element 2 to the output 15

3

devices, combined with the output of the control circuit of the digital computer 6 in FIG. 1 is not. shown). The same signal through the element OR 5 transfers the trigger 6 to the single state, while the zero level from the inverse output of the trigger 6 closes the AND 2 element. The signal from the output of the AND 2 element nulls the counter of timer 8, synchronizing its operation with the real trigger period programs.

If during the time T-, to which timer 8 is set, the codes did not coincide at the inputs of the comparison circuit 3, a signal appears at the output of timer 8, which translates trigger 6 into one state, while the zero level with the inverse output of the latter closes the element AND 2, the signal from the output of timer 8 is the start signal for block 4, which in each start period increases the value of the imitation address by step to the step (the initial value of the address is equal to). AT ; In a particular case, the step step may be equal to the length of the command.

Upon the completion of the calculation of the imitation failure address at the output of the operation of block 4, a signal appears that puts the trigger 6 into the zero state, and the unit level from its inverse output goes to the second input of the AND 2 element.

When the codes on the inputs of the comparison circuit 9 coincide, the signal that transfers the trigger 7 to the zero state, the zero level from its direct output closes the AND elements 1 and the I-2 element and the device completes the software resistance check.

To conduct a program check. on failure resistance on one. A digital computer using the proposed device requires an input information simulator 18 (note that its launch is quite simple to make periodic). The use of a simulator will allow you to compare the results of the program without a connected device and with the connected device checking the programs for failure resistance.

Checking the programs for failure resistance with real input information is possible if there are two digital computers leading parallel processing of the incoming information, with the proposed device connected to one of them.

In addition to conducting a command check of the programs for failure-proofness, the device allows checking the programs by imitation: one-time failure during the execution of a labeled command, which can be provided both by the corresponding task A and at a step step equal to the length of the command and setting the timer 8 for the time of the program being checked as well setting only A tsots with a step of zero equal to zero, and setting timer 8 for the maximum possible time; periodic failure during the execution of the labeled command, while the period is set in timer 8, and the error step is zero;

systematic failure during the execution of the labeled command, while timer 8 is set to T.O, and the step of failure is also zero.

Consider the operation of block 4 address modifications, (Fig. 2).

In the initial state, the step 1 of the entry inputs is entered into register 1 in FIG. 2 are not shown, the pre-zeroed adder 22 is entered on the inputs 21, -24 code A.

When a signal arrives at start 2, it is delayed by the time required to translate trigger 6 into a single state, after which the delay element 23 is used to read the step from the register 19 and supply the code for the step to the counting inputs of the adder 22; The signal delayed by the transients in the adder 22 from the second tap of the delay element 23 is used to implement the carries in the adder. A signal delayed by the realization time of the transfers in the adder 22 and by the response time of the circuit 9 of the comparison appears (at the output 27 of the end of work.

The use of new elements and new connections in the proposed device favorably distinguishes it from the prototype, as it allows to expand the functionality by providing the ability to check for failure resistance of cyclical program areas and the possibility of command-by-check programs for failure resistance in the automatic mode.

Claims (2)

Invention Formula 1. A device for testing fault tolerance programs containing the AND element, the OR element, the first and the third triggers, the first comparison circuit and the final address register, and the comparison output of the first comparison circuit is connected to the first input of the AND element, which differs from In order to expand the field of application of the device by means of both T1 of the possibility of checking cyclic programs, the second comparison scheme, the group of elements I, the timer and the address modification block are entered into the device, the device’s address inputs being connected to the first and elements AND groups whose outputs are connected to the corresponding inputs of the first group of inputs of the first comparison circuit, comparison code of the first comparison circuit is connected to the first input of the OR element, the output of which is connected to the single input of the first trigger, the inverse output of the first trigger AND , the output of which is connected to the timer recording input and is the device recovery unit, the group of inputs of the address address modification block% connected to the input group of the device’s initial address setting, the group of outputs the address modification block is connected to the second group of inputs of the first comparison circuit and the first group of inputs of the second comparison circuit, the comparison output of which is dinen with the zero input of the second flip-flop, the inputs for setting the final address of the device are connected to the information-inputs of the register of the final address, the group of information outputs of which is connected to the second group of inputs of the second comparison circuit, the start-up input of the device is connected to the single input of the second flip-flop, direct output which is connected to the second inputs of the elements AND of the group, to the third input of the element AND, to the start input of the timer, the output of the end of the time interval which is connected to the second input of the element OR and the input start in the address modification block, the exit is ending. whose work is connected to the zero input of the first trigger. 0 2. The device according to d. 1, that is, that the address modification block contains a register, adder, a group of elements AND, a group of elements OR, and a delay element, with the first input of the elements OR of a group connected to the corresponding inputs of the group of inputs of the block, the second inputs of the elements OR of the group are connected to the outputs of the corresponding elements AND of the group, the first inputs of which are combined and connected to the first output of the delay element, the second inputs of the elements of the AND group are connected to the corresponding bit outputs of the register, the outputs ENTOV OR groups are connected to the respective information inputs of the adder, which output group is a group unit outputs: carry input of the adder coupled to the second output of the delay element, a third output which is the output end of work unit. . tf, t-rif. 0 five J, t:; fy . X TT I I3a  -.a, v, / x,; / g / 2 {) - p 24; / Lg / 5, FIG. 2, Fm.z Editor M.Kelemes Compiled by I.Sigalov Tehred A.Ach Order 8536/51 Circulation 709Subscribe VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, F-33, Raushsk nab., 4/5 Branch PPP Patent, Uzhgorod, Proektna St., 4 Proofreader G. Reshetnik