SU1192167A1 - Buffer storage for processing television signals - Google Patents

Description

The invention relates to television and can be used in digital proofreaders temporal distortion of television signals, reproducing from a VCR. five

The purpose of the invention is to reduce signal distortions that occur at non-nominal speeds of the video tape.

FIG. 1 shows a structural 10 circuit diagram of a buffer memory device for processing television signals; figure 2 diagrams explaining the operation of the device. ,five

The buffer storage device for processing television signals contains a block of 1 buffer memory, the information input of which is the first input of the device, 20

output - device output, write address of the block 1 of the buffer memory and information input of the first shaper 2.The gates are combined and connected to the output of the counter 25 3 write addresses, the address input of the block 1 of the buffer memory and the information input of the second shaper 4 of the strobe are combined and connected to the output the counter of 5 addresses of readout, the clock input of the block 1 of the buffer memory and the clock input of the counter 3 of the write address are ^1- connected and connected to the output of the first key block 6, the clock input of the block 1 of the buffer of memory

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and the clock input of the read address counter 5 is combined and connected to the output of the second key block 7, the first shaper 8 of the start of counting signal, the setup input of which and the setup input of the record address counter 3 are combined and connected to the output of the first shaper of 9 lower case pulses the inputs of the first key block 6 and the first driver 8 of the start counting signal are combined and connected to the output of the first driver 10 clock pulses, and the output of the driver 8 of the start counting signal through ne strobe driver 2 is connected to the control input of the first key block 6, sync selector 11, the input of which is the second device input, first clock output connected to the input of the first driver 10 clock pulses, second clock output to the clock input of the playback pulse counter 12, first control output - to the second and first input, respectively, of the first 9 and second 13 shaper pulse formers, and the second control output to the first input of the shaper 14 frame pulses, the second driver 15 signal of the beginning of the account, the installation input of which and the installation input of the counter 5 addresses of reading are combined and. connected to the output of the second 192167

the driver of 13 horizontal pulses, the clock inputs of the second key block 7, the second driver of the 13 horizontal pulses and the driver of 14 frame pulses are combined and connected to the output of the second driver of 16 clock pulses, and the output of the second driver of 13 horizontal pulses through the second driver of the 4 gate - ^10-governing controlled to the second key entry unit 7, the timing generator 17, a first clock output is connected to an input of the second clock generator 16, and the second takto- '5 ^ vy output - to the clock output with etchika reference pulses 18 whose carry output is connected to a second control input of the third gate driver 19, the output of counter 18 20

the reference pulses through the decoder 20 is connected to the control input of the comparator unit 21, the first and second outputs of which are respectively connected to the first and second control inputs of the second driver 15 of the counting signal, the first control input of the third driver 19 of the gate is connected pulses, the perimeter output of the third gate driver 19 to the enable input of the counter 12 playback pulses, and the second output to the enable input of the counter 18 reference pulses, you-35 the progress of the counter 12 replay pulses connected to the information input unit 21 comparison.

The device works as follows. 40

The television signal reproduced at a certain speed of the video tape motion in the form of a digital stream parallelized to the w channels is fed to the input of block 1 of the buffer memory, built on special memory chips with random access, having separate address and clock inputs for recording and reading. The operation of the device consists in 50 equalizing the duration of the active reproduced line to the nominal value due to the distortion of the blanking time interval while maintaining the total duration of the reproduced television line constant. The active part of the reproduced television line is extracted using a gate formed by the first gate generator. For this, an auxiliary counter located in the first shaper 8 of the start counting signal counts a predetermined number of clock pulses from the leading edge of the pre-phased 9 horizontal pulses of the reproduced string pulse to the beginning of the active part of the string previously phased in the first shaper. When this point is reached, a pulse is generated in the first shaper 8 of the start of counting signal that triggers the first strobe shaper 2, which opens the first key block 6, which allows the first and subsequent bits to be recorded that carry information about the active part of the playback line in the buffer memory 1 ′. The moment the last bit of the active part of the line arrives in block 1 of the buffer memory, the decoder located in the first gate generator 2, upon receipt of the corresponding code combination from the counter 3 write addresses, generates a pulse that terminates the write gate. The first key block 6 is closed, which prohibits writing to the block 1 of the buffer memory before the start of the next active part of the line of the television signal.

When forming a read strobe, an auxiliary counter, which is part of the second shaper 15 of the start counting signal, in addition to the number of reference clock pulses that fit before the start of the active line, counts the number of pulses determined by the commands of the comparison unit 21 in addition to the number of reference clock pulses.

The sign of the mismatch of the reproduced and reference frequencies is determined at the beginning of each line of recording (at the beginning of each image field). To do this, on command, coming from the imaging unit 14 frame pulses, the third imaging unit 19 strobe opens the counter 12 playback pulses and the counter 18 reference pulses. The counter 12 of the playback pulses starts counting the reproduced high frequency clock pulses, the code information about the current state

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at its outputs all the time is fed to the input of block 21 comparison. At the same time, the counter 18 pulse reference starts. Unlike the counter 12 playback pulses, it counts a strictly defined number of reference clock pulses of high frequency, at which the decoder 20 generates a control pulse, also arriving at the unit 21 of the comparison. This command compares the readings of the counter 12 playback pulses and the internal register of the comparator unit 21, into which a number has already been written, which coincides with the number of 18 reference pulses of clock pulses counted by the counter. The result of this comparison and is transmitted to the inputs of the second driver 15 of the signal to start the account.

The plot a (Fig. 2) shows the case when the reproducible frequency £ _{k is} greater than or equal to the reference £ ₀ .

In this case, the reading of information from the first cells of the block 1 of the buffer memory in each of the parallel channels starts already during the process of writing data to the initial cells. Plot 5 reflects the situation when £ _c C £ ₀ . Here, the process of reading from the first cells of block 1 of the buffer memory begins only during the recording of information in the last cells.

The appearance of the transfer pulse counter 18 reference pulses at the second input of the third driver 19 strobe stops the counter 12 and the playback pulses and the counter

18 reference pulses. During the entire current image field, the auxiliary counter located in the _5th second generator 15 of the start of counting signal counts the number of pulses corresponding to 10 to the command issued by the comparison unit 21, in addition to the number of reference clock pulses placed before the beginning of the active line. Upon reaching the target thus set. time in the second generator 15 of the signal of the beginning of the counting, a pulse is generated that triggers the second second generator 4 of the strobe, which opens the second key block 7. This allows reading the first and subsequent bits carrying information about the 20 line being played back from block 1 of the buffer memory.

At the moment of reading the last bit of the active line from the buffer memory block 1, the decoder located in the second gate builder 4, by acquiring the corresponding code combination from the counter of 5 read addresses, generates a pulse that terminates the read gate. The second key block 7 closes,

30 which prohibits reading from block 1 of buffer memory.

The proposed device allows for maintaining the initial information capacity of the buffer memory block to provide twice the range of correction of frequency mismatches that occur at non-nominal speeds of video tape (such as freeze-frame, accelerated and slow playback in forward and reverse fusing).

1192167

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Claims (1)

BUFFER STORAGE DEVICE FOR PROCESSING TELEVISION SIGNALS containing a block of buffer memory, information input of which is the first input of the device, output - output of the device, address entry input of the block of buffer memory and information input of the first strobe driver are connected to the output of the write address counter, address input input the buffer memory block and the information input of the second gate driver are combined and connected to the output of the read address counter, the clock input of the block b Fern 'memory. and the clock input of the write address counter are combined and connected to the output of the first key block, the read clock input of the buffer memory block and the clock input of the read address counter are combined and connected to the output of the second key block, the first shaper of the beginning of the counting signal, the setup input of which and the setup input of the write address counter are combined and connected to the output of the first horizontal pulse shaper, whose clock input and the clock inputs of the first key block and the first counting signal generator are combined and connected to the output of the first clock pulse generator, and the output of the first counting signal generator through the first gate generator is connected to the control input of the first key block, the sync selector whose input is the second input of the device, the first the clock output is connected to the input of the clock pulse shaper, the first control output is connected to the second input and the first entrance respectively the first WITH second and second control output to the first input of the personnel pulse generator, the second generator of the start of counting signal, the setup input of which and the installation input of the read address counter are combined and connected to the output of the second horizontal pulse former, clock inputs of the second the key block, the second horizontal pulse generator, and the frame pulse generator are combined and connected to the output of the second clock generator, and the output of the second generator ovatelya lowercase pulses through the second gate driver -. for the second control input key unit, the timing generator, a first clock output is connected to the input of a second clock pulse generator, characterized in that, in order to reduce signal distortion arising in nenominalnyh 5i, „, 1192167 one 1,192 video tape speeds, a playback pulse counter, a reference pulse counter, a third gate driver, a comparison unit and a decoder are entered into the device, the first control input of the third gate driver is connected to the frame pulse driver output, the second control input is connected to the transfer output of the reference pulse counter, the first output is to the enable input of the playback pulse counter, and the second output is to the enable input 167 ' the reference pulse counter, the clock input of the playback pulse counter is connected to the second clock output of the sync selector, and the output is connected to the information input of the comparator, the clock input of the reference pulse counter is connected to the second clock output of the clock generator, and the output through the decoder to the control input of the comparator, the first and second the outputs of which are connected, respectively, to the K'Pervom and to the second control inputs of the second shaper of the signal to start the counting. one