SU1161892A1 - Digital meter of radio pulse basic frequency - Google Patents

Abstract

DIGITAL MEASURER RADIO IMPULSE COMPLETION FREQUENCY, containing a clock pulse generator, a driver connected to the meter input, first trigger, first, second And elements, measured frequency counter, clock counter, additional counter and first divider, setting, inputs of which are connected to the additional outputs the counter, the output of the first divider is connected by the R input of the first trigger, the S input of which is connected. with the output of the imaging device and through the delay element connected to the installation input of the additional counter, the direct output of the first trigger is connected to the first input of the second element I, the output of which is connected to the counting input of the first divider, characterized in that, in order to improve the accuracy, it is entered the second frequency divider, the second trigger, the third element I, the element 3-ЗИ-ШШ, the first one, the second memory registers, the coder, accumulating adder and line draw}, the input of which is connected to the output of the clock pulse generator c, the outputs of the delay line are connected by EE-inputs of the first and second registers and with the first inputs of the .3-ZI-OR element, the second inputs of which are connected to the outputs of the first memory register and the first group of inputs of the encoder, the second group of inputs of which are connected to the outputs of the second register the memory, the output of the encoder is connected to the inputs of the accumulating adder, the outputs of which are connected to the setup inputs of the second divider, the control input of which is connected to the output of the clock counter, the counting input of the second divider n with counting inputs of a clock counter and an additional counter, with the second input of the second element AND and the output of the 3-ZI-OR element, the third inputs of which (connected to the output of the second trigger, whose input is connected to the additional output of the additional counter, 5 - the input is connected to the control inputs of the clock counter and an additional counter, to the first input of the third element I and to the direct output of the first trigger, the inverse output of which is connected to the control input of the accumulating adder and s.pe The first input of the first element is And, the second input of which is connected to the C-input of the second register, to the second input of the third element And and the output of the imager, whose blocking input is connected to the output of the second divider, the output of the first element And is connected to the C-input of the first register memory ti, the output of the third element And is connected to the counting input account

Description

The meter of the measured frequency and the input is the recording of the first divider, and the control 1161692 is the input of the clock counter connected to its inverse output.

The invention relates to a measurement technique and can be used to measure the frequency of filling of radio pulses. A device is known comprising a reference generator, time selectors, a detector, a driver, a trigger, a counter and a driver, a time interval consisting of a counter, a code adder and a memory element that performs the formation of a time interval from video pulses, the duration of which is a multiple of the repetition period of measurements impulses l. The disadvantage of this device is low accuracy. The closest in technical essence to the foregoing is a device for measuring the frequency of filling of radio pulses, containing the element And, the reference frequency counter, the counter of the measured frequency, driver, trigger, reference frequency generator, the output of which is connected to the first input of the element And, the second input connected to the trigger output, the S input of which is keyed to the output of the driver, the first input of which is connected to the input bus of the device, and also contains a delay element (one-shot), an additional element And, to Fill in the counter and divider, the counting input of which is connected to the first input of the additional element I, with the counting input of the additional counter and with the output of the element I, the recording input of the divider is connected to the installation INPUT of the additional counter, WITH the counting input of the measured frequency counter and with the output shaper, the output of the divider is connected to the R-input of the trigger, the output of which is connected to the input of the delay element whose output is connected to the second input of the additional element I, the output of which is connected to the counter reference impulse The output of which is connected to the second input of the imager, while the outputs of the additional counter are connected to the additional inputs of the divider 2. A disadvantage of the known device is low measurement accuracy in the case when the measured frequency is comparable with the frequency of the clock generator, since there is no synchronization between the measured pulses and the clock pulses. This leads to the fact that on the interval between the first and last measured pulses of a bundle, an error in calculating clock pulses depending on phasing can be an 11 clock pulse, and when drawing up a time interval from H packets of radio pulses, the error can reach the value -MTD, therefore actual. The time interval T is equal to T ± NTg, where T is the period of clock pulses, and the value of the time interval being formed is random and obeys the normal law. If the measured carrier frequency is commensurate with the clock frequency, then the measurement error is also significant. The purpose of the invention is the measurement accuracy. The goal is achieved by the fact that the first trigger, the first, the second And elements, the meter of the measured frequency, the counter of clock pulses, the additional counter and the first divider, the adjustments the inputs of which are connected to the outputs of the additional counter, the output of the first divider is connected to the R input of the first trigger, the S input of which is connected to the output of the driver and through its delay element dinene with the installation input of the additional counter, the direct output of the first trigger is connected to the first input of the second element AND, the output of which is connected to the counting input of the first divider, the second frequency divider, the second trigger, the third element AND, the element 3-ZI-OR, the first second memory registers, an encoder accumulating sum1; an ator and a delay line whose input is connected to the output of the clock generator; the outputs of the delay line are connected to the first and second registers and to the first inputs of the 3-ZI-OR element; first connected to the outputs of the first memory register and the first group of inputs of the encoder, the second group of inputs of which is connected to the outputs of the second memory register, the outputs of the encoder are connected to the accumulator hoppers (memory adder, the outputs of which are connected to the installation inputs of the second divider, whose control input is connected to the output of the clock counter, the counting input of the second divider is connected to the counting inputs of the clock counter and an additional counter, with the second input of the second element And and the output element The 3-ZI-ShSh, the third inputs of which are connected to the output of the second trigger, the R input of which is connected to the additional output of the additional counter, the 5 input is connected to the control inputs of the clock counter and the additional counter, and with the direct output of the first trigger, the inverse output of which is connected to the control input of the accumulating adder and the first input of the first element And the second input of which is connected to the C input of the second register, with the second input of the third element And the output of the forms The interrogator, whose blocking input is connected to the output of the second divider, the output of the first element I is connected to the C input of the first memory register, the output of the third element I is connected to the counting input of the counter of the measured frequency and the recording input of the first divider, and the control input counter clock pulse is connected to its inverse output. 924 FIG. 1 shows a block diagram of a digital meter for filling the frequency of radio pulses; in fig. 2 - diagrams illustrating his work. The digital meter for filling the frequency of radio pulses contains a generator of 1 clock pulses, a delay line 2, the first memory register 3, in which in accordance with the three. the information inputs are called the) inputs and the record input as the C input; 3-ZI-IPI 4 element, 5 clock pulse counter, first Divider 6, driver 7, first trigger 8, first And 9 element, first And 10 element, measured frequency counter 11, frequency element 12, 1 / delay element, additional counter 13, second element AND 14, second divider 15, second trigger 16, second memory register 17, encoder 18, accumulating adder 19. Generator 1 output is connected to line 2 input, whose outputs are connected to information inputs of registers 3, 17 and to the first group of inputs of element 4, the second group of inputs of which is connected to the first a group of inputs of the encoder 18 and connected to the outputs of the register 3, element 4 is connected to the second input of the element 14, to the counting inputs of counters 5, 13 and the divider 15, the control input of which is connected to the output of the counter 5, the inverse clock of which is connected to the control input this counter. The output of the divider 15 is connected to the blocking input of the imaging unit 7, the input of which is connected to the input of the meter, and the output of the imaging device 7 is connected to the first inputs of the And 9 and 10 elements, with the S input of the trigger 8, with the recording input 17 and through the element 12. with the installation the input of the counter 13. The output of the trigger 8 is connected to the second inputs of the elements 10, 14, with the S input of the trigger 16 and with the control inputs of the counters 5, 13, the inverse output of the trigger 8 is connected to the control input of the accumulating adder 19 and the second input of the element I 9 whose output is connected to in the course of the register 3. element 10 is connected to the counting input of the counter 11, to the recording input of the divider 6, the counting input of which is connected to the output of the temporary selector 14, the installation inputs of the divider 6 are connected to the outputs of the counter 13, and the output of the divider 6 is connected to the trigger input 8. Additional output of the counter 13 is connected to the R-input of the trigger 16, the output of which is connected to the control input of the element 4, and the outputs of the register 17 are connected to the second group of inputs of the encoder 18, the outputs of which are connected to the inputs of the accumulating adder 19, the outputs of which are connected to the set The ovine inputs of the divider are 15. In FIG. 2 shows the following timing diagrams: 20 - pulses at the output of generator 1; 21 - pulses at the outputs of line 2; 22 - signal at the input of the meter; 23 - pulses at the output of the imager 7; 24 is the signal at the output of the trigger 8; 25 - pulses at the output of the element And 9; 26 - pulses at the output of the element And 10; 27 - pulses at the counting input of the divider 6; 28 - the signal at the output of the trigger 16; 29 - pulses at the output of element 4; 30 - the signal at the output of counter 5 (the actual number of pulses counted by the counter 5 in the interval of one bundle of input radio pulses is also shown); 31 signal at the output of divider 15 (also shown is the number of pulses T corresponding to the code on the installation inputs of divider 15 formed by adder 19 by summing the codes from the outputs of the encoder 18 corresponding to the interval between the last clock pulses and the measured pulses of each burst); 32 - formed time interval. The digital frequency meter of the radio pulses operates as follows. Triggers 8, 16, registers 3, 17 of memory, counters 5, 11 and 13, dividers 6 and 15 are set to the zero state (installation circuits are not shown in the diagram) are installed at the initial measurement time. As a result, a unit potential is formed at the inverse outputs of the counter and divider 15. No.1 pulses 20 from the generator output arrive at line 2, from the outputs of which the pulses 21 are removed, shifted relative to each other by the value of TQ / n, where n is the number of outputs of the delay line 2. The radio pulse bursts 22 arrive at the input of the imaging unit 7, which is open at the control input for a predetermined measurement interval and forms short positive pulses 28. The first clock. impulse 23 of the first pack through the element I 9 sets the one state of that bit of the register 3 of the memory which has an information input to this mono. The ment has a single potential. The unit potential recorded in the corresponding register memory register 3 memory at the time of arrival of the first h.ch. during the first packet of input radio pulses the passage of clock pulses 21 through element 4 to the input of the counter 1 and 5 clock pulses forming the time interval from the output of the delay line 2 at which the clock pulse occurred at the moment of arrival of the first. h pulse packs. Thus, synchronization of the first i.e. impulse 23 packs of radio pulses and clock pulses 21. In addition, the first B.ch. pulse 25 of the first packet, the counter 13 is set to the state corresponding to the code of a certain number K (for example, K 2 or 3), the trigger 8 is set to one state, opens the elements 10 and 14, sets the counters 5 and 13 to the add mode and translates the trigger 16 into a single state, as a result of which the element 4 is opened and the clock pulses 29 begin to arrive at the inputs of the counters 5, 13 and the divider 6, however, in the interval between the first and second r.h. the pulses 23 of the first packet of the divider 6 do not read iact pulses 29, since the zero code is written on its installation inputs. With the arrival of the second century. the pulse 23 of the first packet in the register 17 of the memory is performed by fixing the states of the delay line 2 at the moment of arrival, the second h.ch. pulse and record on the installation inputs of the divider 6 code of the number of clock pulses, counted by the counter 13 on the interval between the first and second inc. pulses, taking into account the initial installation of the counter 13. The same impulse, somewhat delayed, sets the counter 13 to its initial state, corresponding to the code of a certain number K. In the interval between the second and third century. the pulses of the first packet, as well as between subsequent high-voltage the pulses of this packet, the counter 5 counts the clock pulses 29 to form a time interval 30, the counter 13 counts the clock pulses 29 according to the initial setting, and the divider 6 taking into account the set division factor by the installation inputs. In this case, the overflow of the divider 6 does not occur, since the number of clock pulses received at its counting input between the vol. by pulses 23, less by the K value of the number written by the set inputs. Each incl. the impulse 23 of the first packet in register 17 of memory was performed by fixing the states of the 2-delay line at the moment of arrival of the input r.p. im pulse. The encoder 18 encodes the states of the memory registers 3 and 17, and on the encoder 18, the binary code of the difference of the numbers of unit bits of the memory registers 3 and 17 is generated. At the time of receipt of the last century. pulse 23 of the first packet at the output of the encoder 18, the binary code of the difference of the unit bits of registers 3 and 17 is formed, fixing the state of the delay line 2 at the moment of the first and last rh. pulses 23 of the first pack. This code corresponds to the difference between the period of clock pulses Td and the interval between the last clock pulse 29 before the arrival of the last B.Ch. the impulse of the first packet and the last v.ch. impulse 23, if the period TQ is expressed by a binary code of the number n, equal to the number of outputs of the line 2, the delays, and the interval between the last ones is clock and i.ch to express the binary code of the unit bit of the line 2 delay. The maximum number that can be at the outputs of the encoder is equal to the number n and is formed when the clock pulse coincides with the last rpm. For example, when the third digit of the four-bit register of memory 3 is in the unit state and the unit of the third (fourth, first, second) digit of the four-digit memory register of 17 in the encoder 18 outputs a code of 100 (011, 010, 001 ). The accumulating adder 19 in the pause between the first and second pack 23 summarizes this code with the zero code that was at the output of the encoder 18 before the measurement began. After the arrival of the last century. the pulse of the first pack at the output of the divider 6 when calculating the number of clock pulses 27 equal to the established division factor, a differential is formed, which sets the trigger 8 to the zero state. Here, the arrival of the clock pulses 27 through the time selector 14 is stopped. When the trigger 8 is set to the zero state, the pulse number from the output of the divider 6 in the counter 11 is calculated. pulses 26 of the first pack (except for the first pulse of the pack), the counter 13 counted the number of clock pulses 29 received at the counting input in the interval between the last rpm. the pulse of the first packet and the trailing edge of the pulse 24, and in the counter 5 the number of clock pulses 29 received at the counting input in the interval between the first and the last r.h. pulses and between the last v.ch. a pulse and a falling edge of pulse 24. In the pause between the first and second bursts of radio pulses, trigger 8 is in the zero state and blocks the time selectors tO and 14, and counters 5 and 13 operate in subtraction mode. When the counter | 3 counts the number of clock pulses 29 recorded in the counter 13 at the moment of switching the reverse, a differential is formed at the output of the counter 13 borrowing, which sets the trigger 16 to the zero state. In this case, the element 4 is closed at the control input and the flow of the clock pulses 29 to the inputs of the counters 5 and 13 is stopped. Thus, in the interval of the first burst of radio pulses, the counter 5 counted the clock pulses only in the interval between the first and the last rf pulse of the burst (see plot 30), with the first clock pulse synchronized with the first rpm. impulse, and in accumulator 19 is fixed a code defining an interval equal to

the difference between the period T of clock pulses and the interval between the last calculated clock pulse and the last in, h impulse of the first pack. With the arrival of the first B.CH. the pulse of the second packet through the time selector 9 in the memory register 3 fixes the outputs of the delay line 2 at the moment of the arrival of the first bh. impulse of the second pack and installation of the trigger 8 into one state. In this case, similarly as in the first pulse train, counters 5 and 13 are transferred to the addition mode, element 10 is opened, trigger 16 is set to one state, counter 13 is set to the state corresponding to the code of a certain number K, element 4 is opened , the inputs of the counters 5 and 13 and the de-dial 6 begin to receive the clock pulses 29, synchronized with the first clock. pulse of the second pack, and on the installation inputs of the divider 6 recorded code. equal to the number of clock pulses, counted by the counter 13 on the interval between the penultimate and last r.h. pulses of the first pack.

During the operation of the second and subsequent bursts of radio pulses, a similar counting of the measured pulses 26 by the counter 11, the clock pulses 28 by the counter 5 and the generation of the control pulses 24, 28 by the counter 13, divider 6, triggers 8 and 16 is performed. The actual interval between the last clock pulse the pulse counted by the counter 5 during the operation of the previous radio pulse and the first clock pulse synchronized by the first r.h. the pulse of the pulse of the radio pulse packet and the counted counter 5 always turns out to be less than the period T. of clock pulses and when the last clock pulse coincides with the last pulse of the previous packet, it is zero. In this case, in the pause, the maximum number equal to n is formed at the outputs of the encoder 18, since the actual interval between the last clock pulse of the previous burst and the first clock pulse of the subsequent burst is zero.

In accumulator adder 19, in caddy i, the pause between pulses 24 is the summation of codes from the output of the encoder 18 with the codes that occurred at the outputs of the encoder during 1+ (i-1) pauses, and the formation of codes as an integer number of pulses Tr.

When the counter 5 counts the number of clock pulses 29 corresponding to the selected measurement interval, a single potential is formed at the output of counter 5, which allows the arrival of clock pulses 29 at the counter input of the divider 15 and blocks the arrival of clock pulses at the input of the counter 5 with an inverted zero signal. However, the generated time interval 30 at the output of the counter 5 is less than the required time interval 32 by the number of periods T of clock pulses, equal to the binary code at the output of the accumulating sum. At the moment of forming a single difference, at the output of the counter 5. This code with the output of accumulating adder 19 is fed to the installation inputs of the divider 15 and when this divider is counting the number of clock pulses 31 equal to the number at the installation inputs, the inverse output of the divider 15 forms a zero potential blocking driver 7. In this case, the flow of measured incl. the pulses to the input of counter 11 are terminated. After the last measured pulse passes through shaper 7, a pulse is formed at the output of divider 6 when counting the number of clock pulses equal to the set division factor, which sets the trigger 8B to zero status. The counter 13 is transferred to the subtraction mode, and at the time of the formation of the differential at the output of the counter 13, the trigger 16 sets the B state to zero and blocks the arrival of clock pulses through the time selector 4.

Accuracy in the invention is enhanced by synchronization of the first clock and B.ch. radio pulses in each burst. pulses and taking into account the interval between the last century. the burst pulse and the preceding clock pulse, which eliminates the error in the formation of the time interval associated with the discreteness of the clock frequency

Improving the accuracy of forming the time interval makes it possible to measure the frequency of a full-frequency oscillator, which allows you to increase the range of measured frequencies without increasing the frequency of the clock geo input

The effectiveness of using a digital meter in a wider frequency range of input signals.

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Claims (1)

RADIO PULSE DIGITAL FREQUENCY METER, comprising a clock pulse generator, a shaper connected to the meter input, a first trigger, a first, second AND element, a measured frequency counter, a clock pulse counter, an additional counter and a first divider, installation inputs of which are connected to the outputs of the additional counter, the output of the first divider is connected to the R-input of the first trigger, S-input of which is connected. with the output of the shaper and through the delay element connected to the installation input of the additional counter, the direct output of the first trigger is connected to the first input of the second element And, the output of which is connected to the counting input of the first divider, characterized in that, in order to increase the accuracy of measurements, the second frequency divider, second trigger, third AND element, Z-ZI-OR element, first, second memory registers, encoder, accumulating adder and delay line, the input of which is connected to the output of the clock generator, output the delay line odes are connected with the cD inputs of the first and second registers and with the first inputs of the .Z-ZI-OR element, the second inputs of which are connected to the outputs of the first memory register and the first group of encoder inputs, the second group of inputs of which are connected to the outputs of the second memory register, outputs the encoder is connected to the inputs of the accumulating adder, the outputs of which are connected to the installation inputs of the second divider, the control input of which is connected to the output of the clock counter, the counting input of the second divider is connected to the counting and the inputs of the clock counter and the additional counter, with the second input of the second AND element and the output of the З-ЗИ-OR element, the third inputs of which ^{1 are} connected to the output of the second trigger,!? - the input of which is connected to the additional output of the additional counter, 5 - the input is connected to the control inputs of the clock pulse counter and the additional counter, with the first input of the third AND element and with the direct output of the first trigger, the inverse output of which is connected to the control input of the accumulating adder and the first the input of the first element And, the second input of which is connected to the C-input of the second register, with the second input of the third element And and the output of the driver, the blocking input of which is connected to the output of the second alternator, the output of the first element And is connected to the C-input of the first memory register, the output of the third element And is connected to the counting input of the counter SU _П11 1161892 of the measured frequency and the input of the input of the clock counter of the first divider, and the control is connected to its inverse output .