SU1160417A1 - Device for checking digital units - Google Patents

Abstract

1. DEVICE FOR CONTROL OF DIGITAL KNOTES, containing a pulse generator, test generator, selector, signature analyzer, synchronization unit, control unit, memory unit, comparator unit, two AND elements, and the code of the pulse generator and the unit synchronous input synchronization, the setup inputs to the initial state of the synchronization unit, the test generator, the control unit, the signature analyzer, the tested node are combined and are the setup input to the initial state of the device, The test generator generator inputs are connected to the input group of the tested node, the output groups of which are connected to the group of information inputs of the selector, the control group of the two inputs of which are connected to the output group of the control unit and the group of input readings of the memory unit whose output group is connected to the first group the inputs of the comparison unit, the rotor, the group of inputs of which is connected to the group of outputs of the signature analyzer, whose information input is connected to the output of the selector, the synchronous input of which is connected to The first output of the synchronization unit, characterized in that, in order to improve the control performance, a modulo two convolution unit, an addition element But moduli two, a trigger, an indicator are inserted into it, the output group of the tested node is connected to the modulus convolution unit input group two, the output of which is connected to the information input of the selector, the control input of which is connected to the clock output of the control unit, the contact input of the block (L memory, the first input of the first element AND and the first input of the addition element There are two, the second input of which is connected to the output of the comparison unit and the second input of the first element I, the third input of which is connected to the second code of the synchronization unit and the first input of the second element I, the second input of which is connected to the code of the addition element of 4 , the output of the second element V I is connected to the synchronous input of the control unit, the installation input of the device is connected to the zero input of the trigger, a single input of which is connected to the output of the first element I, the output of the trigger is connected to the input of the indicator, and for controlling comprises a counter and decoder, wherein the installation control unit input is connected to the mounting vho- counter house sknhrovhod which is a clock terminal block, a group of counter outputs are connected with the group

Description

Understanding the inputs of the decoder, the first output of which is the clock output of the control unit, the group of outputs of the decoder second to (t + 1), is the output group of the control unit,

2. The device according to claim 1, wherein the synchronization unit comprises a counter, a decoder and an OR element, wherein the installation input of the block is connected to the installation input of the counter, the synchronous input of which is connected to the control input of the decoder, and the group of output of the counter is connected with the group of information inputs of the decoder, the outputs of which from the first to the nth are connected respectively with the inputs of the OR element, the output of which is the first output of the device,

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the output of the decoder is the second output of the block,

3. The device according to claim t, characterized in that the signature analyzer contains a shift register, a modulo two convolution node, a delay element, the information input of the signature analyzer connected to the modulo two input of the convolution node, the input group of which is connected to the first group of register outputs the shift, the second group of outputs of which is the group of outputs of the signature analyzer, the installation input of which is connected to the installation input of the shift register, the synchronous input of which is connected to the output of the delay element whose input It is a clock terminal signature analyzer, An information input shift register connected to the output node convolution modulo two.

one

The invention relates to instrumentation engineering and can be used for monitoring and diagnostics of digital nodes of computer technology.

A device for monitoring and diagnosing digital nodes, comprising a test generator, a memory block, a signature analyzer and an indicator 1, is known.

The drawback of the device is low productivity, since to evaluate the operability of a digital node, it is necessary to manually check the signature convolutions in the o, checkpoint,

The closest technical solution to the present invention is a device for detecting malfunctions of digital nodes. It contains a test generator, the first input of which is connected to the output of the pulse generator and the first input of the timer, the second input of the test generator is connected to the first input of the synchronization unit, the second input of the timer, the first input of the signature analyzer, the first input of the monitored node and the input

The test run of the device, the outputs of the test generator are connected to the inputs of the monitored node, the output group of which is connected to the first group of inputs of the selector, the second group of inputs of which is connected to the first group of outputs of the synchronization unit and the first group of inputs of the memory unit whose control input is connected to the output of the unit sync and. controlling the input of the memory block whose output is connected to the first input of the first element I, the second input of which is connected to the first output of the timer, the code of the element I connected to the second input of the signature analyzer, the first group of inputs of the comparison block is connected to the output group of the signature analyzer, the second inputs the comparison unit is connected to the outputs of the memory unit, the second element I, the first input of which is connected to the second output of the timer, and the output of the element I is connected to the second input of the synchronization unit 2.

The disadvantage of the known device is the low control performance.

The purpose of the invention is to monitor the performance by obtaining a common node signature that determines its operability, and by eliminating the sequential inspection of the check convolutions at all points in case the common signature coincides with the standard.

The goal is achieved by the fact that the device for controlling digital nodes contains a generator of torques, a test generator, a selector, a signature analyzer, a synchronization unit, a control unit of a memory unit, a terminal unit, two elements, and the input of the pulse generator is connected with the synchronous input of the test generator and the synchronous input of the synchronization unit, the installation inputs to the initial state of the synchronization unit, the installation inputs to the initial state of the synchronization unit, the test generator, the control unit, the signature analyzer, etc. the rotated node is integrated and is the setup input of the device, the output generator group of the test generator is connected to the input group of the tested node, the output group of which is connected to the information input group of the selector, the control input group of which is connected to the output group of the control unit and the group readout inputs of the memory block, the output group of which is connected to the first group of inputs of the comparison unit, the second group of inputs of which is connected to the output group of the signature analyzer, information The main input of which is connected to the output of the selector, the synchronous input of which is connected to the first output of the synchro-onion module, a convolution unit modulo two, an addition element modulo two, a trigger, an indicator are entered, the output group of the tested node is connected to the modulus input unit of the convolution unit two, the code of which is connected to the information input of the selector, the control input of which is connected to the clock output of the read input control block of the block, to the first input of the first element AND and the first input of the addition element

module two, the second input of which is connected to the output of the comparison unit and the second input of the first element I, the third input of which is connected to the second output of the synchronization unit and the first input of the second element I, the second input of which is connected to the output of the adding element modulo two, the code of the second element And connected to the synchronous input of the control unit, the installation input of the device is connected to zero in, the trigger stroke, a single input of which is connected to the output of the first element And, the output

5 The trigger is connected to the indicator input, the control unit contains a counter and a decoder, the installation input of the control unit is connected to the installation input of the counter,

0 the synchronization input of which is the synchronization input of the block, the group of outputs of the counter g is connected to the group of inputs of the decoder, the first output of which is the clock output of the control unit,

5, the second to (tn + 1) -th decoder output group (where tvi is the numerical outputs of the tested node) is the output group of the control unit. The synchronization block contains a counter, a decoder and an OR element, and the installation input of the block is connected to the installation input of the counter, the synchronous input of which is connected to the control input of the decoder and is a synchronous input of the block, the group of outputs of the counter is connected to the group of information inputs of the decoder, the outputs of which are from first to nth connected respectively to the inputs

of the OR element, the jcoToporo output is the first output of the device, the output of the decoder is the second output of the block.

In addition to the toro, the signature analysis j torus contains a shift register, a modulo two convolution node, a delay element, and the information input of the signature analyzer is connected to the modulo two input of the convolution node,

0 the group of inputs of which is connected to the first group of outputs of the shift register, the second rjpynna of whose outputs is the group of outputs of the signature analyzer, the setting

The J input is connected to the shift register setup input, the sync input is connected to the output of the delay element, the input of which J 1 is the synchronization input of the signature analyzer, the information input of the shift register is connected to the output of the convolution node modulo two. FIG. 1 is a diagram of the proposed device, FIG. 2, the synchronization unit, in FIG. 3 — control unit, FIG. 4 - signature analyzer. The device contains a tested node 1, a generator of 2 tests, a generator of 3 pulses, a synchronization unit 4, a control unit 5, a signature analyzer 6, a selector 7, a memory unit 8, a comparison unit 9, an element. And 10, element 11, trigger 12, indicator 13, comparison element 14 modulo DV1, modulo two convolution unit 15 and setup input 16. Synchronization unit 4 contains an encoder 17, an OR element 18 and a counter 19. Control unit 5 contains a decoder 20 and a counter 21. Signature analyzer 6 contains a shift register 22, a delay element 23 and a convolution node 24 two. The device works as follows. At the beginning of operation of the rio device, set input 16 receives a signal that sets the tested node 1, the generator 2 tests, the synchronization unit 4, the control unit 5, the signature analyzer 6 and the trigger 12. In the control unit 5, the first output of the decoder 20 and the output control unit setup: They are poured into a single state, as a result of which the output of the selector 7 receives information modulo two from the output of convolution unit 15, and the first body into the output of memory unit 8. With the first impulse, a 1M generator of 8 pulses, the first diagnostic layer is set at the output of the test generator 2.. The modulo two convolution unit 15 collapses the multi-bit output response of the monitored node into a single-bit one and through the selector 7 feeds it to the information input of the signature analyzer 6. The first pulse of the generator 3 passes to the first output of the synchronization unit 4 and synchronous input of the signature analysis 76 mountain 6, is delayed on the element 23 delays and fixes the result in the first discharge of register 22 of the shift of the signature analyzer 6. With each subsequent clock pulse, the generator of 2 tests sets at its output a new diagnostic modulated two convolution unit 15 collapses the output response of the monitored node 1, and the shift pulses from the first output of the synchronization unit 4 advance information in the shift register 22, captured by feedback rings, from several register bits to the input of the convolution node 24 module two, .sequentially connected with shift register 22. Upon completion of the full test, the comparison unit 9 sets a single level at its output if the resulting value of shift register 22 of the signature analyzer 6 matches the value of the word at the output of memory block 8, and the zero level in the opposite case, and the synchronization unit 4 outputs from the second output the analyzing pulse, which is fed to the inputs of the first 1 and the second 10 elements I. The signals from the output of the comparison block 9, the output of the control block 5 and the second signal of the synchronization block 4 arrive at the input of the element 11. When these signals coincide, trigger 12 is set to one and indicator 13 signals that the test node is operational. If the resultant convolution of the signature analyzer 6 does not coincide with the value of the word at the output of the 8pam block, then at the output of the convolution block 15 modulo two a unit level is set. Two signals from the convolution unit 15 modulo two and the second output of the synchronization unit 4 are received at the inputs of the And 10 element. When the signals at the inputs of the And 10 element coincide, it produces a pulse to switch the control unit 5. As a result, the control unit 5 connects through the selector 7 the first control point to the information input of the signature analyzer 6 and outputs the second word from the memory block 8 The test generator 2 again issues a test sequence, after which the balance of the signature analyzer 6 is compared with the reference convolution of memory block 8 ti in block 9 comparison. the coincidence of the convolutions of the device 5 proceeds to check the next control point. If the values of the convolutions at the output of the convolution unit 15 modulo two are zero, the And 10 element is closed and the control block 5 10 remains in the position indicating the channel number, the output n604 7 sequence of which does not coincide with the reference one, thereby indicating a malfunction channel. The proposed device provides improved monitoring performance by obtaining a common node signature that determines its operability, and eliminating the sequential viewing of check convolutions at all points in the event that the common signature matches the reference.

FIG. 2

Fig.Z

Claims (3)

' one . DEVICE FOR MONITORING DIGITAL NODES, comprising a pulse generator, a test generator, a selector, a signature analyzer, a synchronization unit the initial settings of the synchronization unit, the test generator, the control unit, the signature analyzer, the node under test are combined and are the input to the initial state of the device, the group of outputs The ode of the test generator is connected to the group of inputs of the node under test, the group of outputs of which are connected to the group of information inputs of the selector, the group of control inputs of which are connected to the group of outputs of the control unit and the group of read and write inputs of the memory block, the group of outputs of which are connected to the first group of inputs of the comparison unit, the second group of inputs of which is connected to the group of outputs of the signature analyzer, the information input of which is connected to the output of the selector, the sync input of which is connected to the first output of the block and synchronization, characterized in that, in order to increase the control performance, a module of convolution modulo two is introduced into it, an addition element rio to module two, a trigger, an indicator, 'and the group of outputs of the node under test is connected to the group of inputs of the convolution unit modulo two, the output which is connected to the information input of the selector, the control input of which is connected to the clock output of the control unit, the read input of the memory unit, the first input of the first AND element and the first input of the addition element modulo two, the second input of which connected to the output of the comparison unit and the second input of the first element And, the third input of which is connected to the second output of the synchronization unit and the first input of the second element And, the second input of which is connected to the output of the addition element modulo two, the output of the second element to AND is connected to the sync input of the control unit , the installation input of the device is connected to the zero input of the trigger, the single input of which is connected to the output of the first element AND, the output of the trigger is connected to the input of the indicator, and the control unit contains a counter and a decoder, Rich installation input control unit connected to the input of the installation counter whose clock terminal is a clock terminal block, a group of counter outputs connected to the group SU.,., 1160417 at the inputs of the decoder, the first output of which is the clock output of the control unit, the group of outputs of the decoder from the second to (tn + 1) -th is the group of outputs of the control unit, 2. The device pop. 1, characterized in that the synchronization unit contains a counter, a decoder and an OR element, wherein the installation input of the unit is connected to the installation input of the counter, the clock input of which is connected to the control input of the decoder and is the clock input of the unit, the group of outputs of the counter is connected to the group of information inputs of the decoder, the outputs of which from the first to the nth connected respectively to the inputs of the OR element, the output of which is the first output of the device, the 2nd ^p- th output of the decoder is the second output of the block. 3. The device according to π. 1, characterized in that the signature analyzer contains a shift register, a convolution unit modulo two, a delay element, wherein the information input of the signature analyzer is connected to the input of a convolution unit modulo two, the input group of which is connected to the first group of outputs of the shift register, the second group of outputs which is a group of outputs of the signature analyzer, the installation input of which is connected to the installation input of the shift register, the clock input of which is connected to the output of the delay element, the input of which is the clock signature analyzer house, information of shift register input connected to the output node convolution modulo two.