SU1140145A1 - Device for reception of information - Google Patents

Abstract

A device for receiving information containing a receiver, a selector of logical zeros, a selector of logical units, a shift register, an OR element, and the output of a selector of logical units connected to the information input of the shift register, characterized in that, in order to increase the reliability of the information received by the device, synchronization selector, elements EXCLUSIVE OR, OR-NOT, NOT, three D-flip-flops, direct and inverse inputs of logical units, direct and inverse synchronization inputs, direct and inverse inputs of logical zeros, the device's control input is the first, second, third, fourth, fifth, second, seventh receiver inputs, respectively; its receiver is connected to the first and second inputs of the logical unit selector with its respective first and second outputs, and the third and fourth outputs are connected to the first and second the inputs of the synchronization selector, the fifth and sixth outputs are connected to the first and second inputs of the logical zero selector, the seventh output is connected to the control input of the shift register, the C input of the first D flip-flop and the first input of the element ENT OR NOT, the output of the logical unit selector is connected to the first input of the EXCLUSIVE OR element, the output of the synchronization selector is connected to the clock inputs of the shift register, the second D-flip-flop and the device sync output, the output of the logical zero selector is connected to the second input of the EXCLUSIVE OR element, whose output connected to the D input of the second D-flip-flop, the device's Input Reset is the S-input of the second D-flip-flop, the R-inputs of the first and i third D-flip-flops and the first input of the OR element, the direct output of the second D-triggers the element is NOT connected to the control output of the device, the inverse output is connected to the second input of the OR element and the S input of the first D-flip-flop, the output of the OR element is connected to the zero input of the shift register, the D-inputs of the first and third D-flip-flops are connected coofBeTCTBeHHO with negative and positive terminals power supply, the direct output of the first Dtrigger connected to the second input of the element OR NOT, the output of which is connected to the output of the third D-flip-flop, the direct output of which is the control output of the device, the outputs of the sdbig register These are the information outputs of the device.

Description

The invention relates to automation and computer technology and can be used in devices of control objects, which are subject to increased requirements for receiving discrete information, and entering the control objects from a computer. A device for receiving discrete information is known, which contains channels of direct and inverse codes, an AND element, an NOT element, an OR element, and an information block consisting of two AND elements and an OR element. The device allows reliable reception of information in the event of interference in one of its channels 1. However, the device is not sufficient; (with an osternality of receiving information, since it can receive information when it is distorted from interference in two channels at the same time. This is a device for receiving information containing a receiver, selectors of code signs pool and units, OR element, register, receiver input, connected to the input terminal of the device, output connected to the input In the case of selectors of code fizpak zero and one, the output of the selector of the code feature of the unit is connected to the first input of the OR element and to the information input of the register, the output of the selector of the code characteristic zero is connected to the second input of the OR element, the output of which is connected to the clock input of the register, the outputs of the register are you device travels. The operation of this device is based on the principle of receiving information from a source of information in the form of a sequential code, the shift register using the allocation of units and zeros of information by the appropriate selectors 2. The disadvantage of the device is its low reliability of reception of information consisting in the absence of a synchronization channel that, if interference occurs in the communication channel, the shift register can receive false information. In addition, OTcyTctBne in the control device receiving information can also lead to the reception of false information. For example, if the effect of interference at the outputs of both selectors will cause ediki. or zero signals, then after the information parcel has been completed, the distorted information will be recorded in the shift register. The purpose of the invention is to increase the reliability of receiving information. The goal is achieved by the fact that the device for receiving information containing the receiver, the selector of logical zeros, the selector of logical units, the shift register, the OR element, the output of the selector of the logic of the zeroes of zeros is connected to the information input of the shift register, the synchronization selector, three triggers are entered , elements EXCLUSIVE OR, OR OR NOT, NOT, direct and inverse inputs of logical units, rf my and inverse enth-synchronization inputs, direct and inverse entrances of logical zeros, the control input of the device are the first, second m, third, fourth, fifth, shchetym, seventh inputs of the receiver, the receiver corresponding to the first and second outputs connected to the first and second inputs of the selector of logical units, the third and fourth outputs connected to the first and second m inputs of the synchronization selector, m. and the common outputs are connected to the first and second inputs of the selector of logical zeros, the seventh output is connected to the main input of the switch. St. the first D-trigger and the first input element AND / 1I-NOT, the output of the logical unit selector is connected to the first input of the EXCLUSIVE OR element, the output of the synchronization selector is connected to the clock inputs of the shift register, D-flip-flop .4;; devices. The cevieKTOpa .augal yih.pey sos; yen f connection is the second input yi e-vieiiTa EXCLUSIVE OR, the output of which is connected to the O input, l: the second 1) trigger, the input device Reset is the S input of the second D flip-flop , the first input of the OR element, 1 -set:.: and the first and third D-flip-flops; the direct output of the second D-flip-flop is NOT connected to the control output of the device, the inverse output is connected to the second input of the OR element and the S-input of the first D-flip-flop, the output of the OR input is connected to the input of the shift register. The O inputs of the first and third D-flip-flops are connected respectively to the negative and positive terminals of the power supply, the direct output of the first D-flip-flop is connected to the second input of the element, the output of which is connected to the C-input t of its D flip-flop, the direct output of which The control output of the device, the outputs of the shift register are the information outputs of the device. FIG. 1 shows a functional diagram of the device; in fig. 2 - functional diagram of selectors 2, 3 and 6. The device contains a receiver, a selector of logical units 2, a synchronization selector 3, an element OR 4, a shift register 5, a selector of logical zeros 6, an element EXCLUSIVE OR 7, the first O-trigger 8, an element NOT 9, the second L-flip-flop 10. element OR-NOT AND, the third D-tr of the generator 12, "minus the power source 13," plus the power source 14, input 15 channel units, inverse input 16 channel units, input 17 of the synchronization channel, inverse entrance 18

synchronization channel, control input of device 19, input 20 of the channel of zeros, inverse noise of 21 channels of zeros, input Reset 22, information outputs 23, control output .24, control output 25, first 26 and second 27 RS triggers, input Selectors 2, 3 and 6, the output of synchronization pulses 28.

The device works as follows.

In the initial state, the shift register is 5 ,. triggers 10, 2, and 27 are in the zero state, triggers 8 and 26 are in the unit state, and zero signals are present at all inputs of the device.

Receiver 1 is designed to match the signals coming from the source of information on the communication lines (inputs) 15-21 with the signals used in this device. Receiver 1 consists of amplifiers, the number of which is equal to the number of its inputs (outputs). In the absence of information at the inputs 15, 17, 19 and 20 and at the corresponding outputs of receiver 1 there are zero signals, and at the inputs 16, 18 and 21 and at the corresponding outputs of receiver 1 -. single

The selectors 2, 3, and 6 are designed to highlight the corresponding attributes of the information, and each of them is constructed according to the scheme shown in FIG. 2. Formation of the information signs at the outputs of the selectors, 2, 3 and 6 can occur only with a corresponding change in the signals at their two inputs. At the same time, at the first input of these selectors, the zero signal should change to a single signal, and at their second input, a single signal, should change to a zero one. When changing the indicated values of the signals at the inputs of the selectors 2, 3 and 6 to the original values, zero signals will again be set at their outputs. Output 28 can be used to control synchronization pulses.

In the proposed device, information is received via two channels — a unit channel consisting of two inputs (communication lines) 15 and 16, and a zero channel, also consisting of two inputs (communication lines) 20 and 21. At that, and information zeros must be accompanied by synchronization impulses received via a synchronization channel consisting of inputs 17 and 18. In addition, the received information is accompanied by a control signal "There is information that arrives at the input 19 of the device.

Before the information arrives at the corresponding inputs of the device, the control input of the device 19 receives a single signal, which, through the corresponding input and output of the receiver 1, enters the control input of the shift register 5, preparing it for sequential reception of units of the information parcel. In addition, this signal is fed to the first input of the OR-NOT 11 element and to the C input of the second trigger 10. At the output of the OR-NOT 11 element, the single signal changes to zero, and the trigger 10 retains its zero state, as it O-VOxT, connected to the "minus power source. When a unit of information is received on a channel,

On the synchronization channel of the sync pulse accompanying it at inputs 15 and 16 and at inputs 17 and 18, the value of the signals changes to the opposite. As a result, at the inputs of selectors 2 and 3, the state of the signals also changes, i.e. at their first entrance,

5, the S-input of the trigger 26 replaces the zero signal with a single signal, and at the second input of the specified selectors and the R-input of the trigger 26, the single signal changes to zero. Therefore, the trigger 26 of the selectors 2 and 3 is switched to the zero state, and the trigger 27 of these selectors is switched to one. A single signal formed at the output of selec-. torus 2, enters the information input of the shift register 5; as a result, the unit is written to the first digit of the last digit

information using the leading edge of a single sync pulse generated at the output of the selector 3. After recording a unit of information and the accompanying sync pulse, the values of the signals at inputs 15-18 and, consequently, at the inputs of selectors 2 and 3 take the initial (initial) state . Since thereafter, at the S input of the trigger 26 of these selectors, the single signal changes to zero, and at its R input, the zero signal

2 changes to one, trigger 26 switches to one state, and trigger 27 to zero. With the subsequent receipt of units of information and the accompanying clock pulses, the operation of the device proceeds similarly. Here, the units of information are written into the corresponding bits of the shift register 5.

When receiving zero information and the accompanying sync pulse at inputs 20 and 21 and inputs 17 and 18, the state of the signals is reversed with respect to their initial state. As a result, at the inputs of selectors 6 and 3, the state of the signals also changes to the opposite of the initial value, and therefore, at the outputs of these selectors, zero signals change to single ones. Since at this time a zero signal acts at the output of the unit selector 2, the zero value of the information signal is written to the corresponding bit of shift register 5 (when

5 this previously received unit of information is shifted by one bit to the right). In the subsequent reception of the zeros of information and the accompanying clock pulses, the operation of the device proceeds similarly. During the reception of information, this device monitors the presence of errors in this information using the EXCLUSIVE OR element 7 and the first D-flip-flop 8. In the absence of errors in the received information, the units and zeros of this information formed at the output of the EXCLUSIVE OR element 7 and arriving at the D input trigger 8, are accompanied by synchronization tO pulses, selected by the synchronization selector 3 and arriving at the C input of the trigger 8. In this case, the single (initial) state of the trigger 8 is confirmed, and the trigger 10 retains its zero (initial) state, since its S input is fed from the inverse output of trigger 8 to a zero signal. Then, after receiving the information parcel, a single signal is taken from the control input of the device 19, as a result of which a single signal OR does NOT change to a zero at the control input of the register of the shift register 5, at the C input of the trigger 10, and at the first input of the terminal OR NOT 11. Since the second input of the element OR HEY 11 also contains a zero "...,, signal, the last one is triggered, and a single signal is generated at its output, which switches the third D-flip-flop 12 to one state. At the output of the latter, and, successively, and at the output 25 of the device, a single control signal is formed, Q which enables the adjacent device to retrieve the received information from the shift register 5. Moreover, this signal goes to the information source to signal that the information has been received that without fault. After removing information 35 from the device outputs 23, the bus 22 receives a single pulse signal Reset, which, through the OR 4 element, zeroes shift register 5, resets the trigger 12 1i to the zero state confirms the initial state of the triggers 8 and 10. The device is ready to receive the next code parcel. Suppose that during the reception of a regular code message, distortions occurred in the communication channels, as a result of which at each input of the selector 2 and the selector 6, the polarity of the signals became the same. In this case, the signals do not change at the outputs of these selectors, since changes to the signals at their outputs can occur only when the signals at their two inputs change. Thus, distortions in one 50 lines of communication cannot lead to a change in the signals at the outputs of the respective selectors, which leads to an increase in the reliability of the reception of information. If in the pauses between the units and the zeroes of the received information, false signals (interference) appear in the information channels of communication, this does not lead to their recording in the shift register 5 due to the absence of the synchronization channel at this time and, therefore, the output selector 3 sync signals. This also leads to an increase in the reliability of receiving information. If, when receiving a regular code message, such distortions have occurred in the information channels, as a result of which the same signal values appear at the outputs of the selector 2 and the selector 6, then a zero signal is produced at the output of the EXCLUSIVE OR 7 element. This leads to the fact that the accompanying synchronization impulse, selected by the selector 3, arrives at the C input of the trigger 8 and resets it to the zero state. As a result, a single error signal appears at the control output 24 of the device, and the single signal from the inverse output of the trigger 8 switches the trigger 10 to the single state and the shift register 5 is reset to the zero state through the second input of the OR 4 element. After the end of the information parcel from input 19, a single signal is removed from the control input of the device. Since a single signal is set at the direct output of the trigger 10, clearing the specified signal does not trigger the elec- tion of the ORENT-NOT 11, and therefore the switching of the triggered. P unit state. Thus, at the considered error in the received information, the device forms on. its control output 24 unit error signal. In this case, the formation of a control single signal at the output. 25 does not occur, which leads to the prohibition of writing off the distorted information from shift register 5 and allowing the source to retransmit the information of the unaccepted code message. The technical and economic effect of using the device in comparison with the prototype is to increase the reliability of receiving information by introducing a synchronization selector, as well as by controlling the reception of information signals, which leads to the exclusion of receiving and issuing false information.

Claims (1)

A device for receiving information, comprising a receiver, a logic zero selector, a logical unit selector, a shift register, an OR element, the output of a logical unit selector being connected to a shift register information input, characterized in that, in order to increase the reliability of receiving device information, synchronization selector, elements EXCLUSIVE OR, OR-HE, NOT, three D-flip-flops, direct and inverse inputs of logical units, direct and inverse inputs of synchronization, direct and inverse inputs of logical zeros, controlling the first input of the device are, respectively, the first, second, third, fourth, fifth, sixth, seventh inputs of the receiver, the receiver with its corresponding first and second outputs is connected to the first and second inputs of the logic unit selector, the third and fourth output is connected to the first and second inputs of the synchronization selector , the fifth and sixth outputs are connected to the first and second inputs of the logic zero selector, the seventh output is connected to the control input of the shift register, the C-input of the first D-trigger and the first input of the OR-NOT element the logical unit selector is connected to the first input of the EXCLUSIVE OR element, the output of the synchronization selector is connected to the clock inputs of the shift register, the second D-trigger and the device synchronization output, the output of the logic zero selector is connected to the second input of the EXCLUSIVE OR element, the output of which is connected to the D-input second D-flip-flop, the input of the “Reset” device is the S-input of the second D-flip-flop, the R-inputs of the first and third D-flip-flops and the first input of the OR element, the direct output of the second D-flip-flop through the element is NOT connected to control output of the device, the inverse output is connected to the second input of the OR element and S-input of the first D-trigger, the output of the OR element is connected with zero input of the shift register, D-inputs of the first and third D-triggers are connected respectively to the negative and positive terminals of the power supply, the direct output of the first D trigger is connected to the second input of the OR-HE element whose output is connected to the Inlet of the third D-flip-flop, the direct output of which is the control output of the device, the outputs of the shift register are information outputs of the device. §I_ <w 1140145