SU1136177A1 - Device for central control of processor unit - Google Patents

Abstract

1. DEVICE OF CENTRAL CONTROL OF THE PROCESSOR, containing a command buffering block, local memory block, counter block, microprogram control block, address broadcast block, address adder, command information registers of the first, second and third levels and first and second item selectors, whose outputs connected to the first and second inputs of the address adder, respectively, the output of which is connected to the corresponding inputs of the address of the local memory block, address translation block and selector of the first term, n The first information input of which is connected to the first information input of the selector of the second term and the information output of the base and index of the local memory block, the first information input of which is connected to the first input of the device control information and the information input of the command buffering block, and the second information input to the second the control information input of the device, the first information OUTPUT of the block of local memory is connected to the first output of the control information of the device, and the second information output the output to the second output of the device control information, the information input of the address translation unit, the information input of the first addendum segment, the micro-outputs of the microprogram control block are connected to the corresponding control inputs of the local memory block, the counter block and the command buffering block, first and second selectors the addends and the address translation block, the input of the external requests of the firmware control block is connected to the input of the external requests of the device - with the corresponding output of the signs of branching of the command buffering block, address accumulator, and address transmission block, the output of the absolute address of which is connected to the corresponding inputs of the absolute J address of the local memory block and command buffering block, outputs of the command information registers, the first, second and third levels are connected to the corresponding information inputs of the multi-directional microprogram block and the front inputs of the local memory, the input of the address of the host of which is connected to the input of the village command torus first term and output of the instruction address counters; the first information which is connected to the output of the first level command information register

Description

It is characterized by the fact that, in order to improve speed, it includes the first, second and third level selectors, the first command address selector, the second command address selector, the third term selector, the communication unit with the operating device and the device memory management, the output of the request of which is connected to the first request input of the device, and the address input to the first information input of the second command address selector and the output of the address adder, the third input of which is connected to the output of the third selector lagging, the absolute address input of which is connected to the absolute address inputs of the communication unit with the operation device and the communication unit with the memory management device and connected to the output / absolute address, the transmission address block, the information input of which is connected to the information input of the communication unit with the device control the memory, the second information input of the second address selector commands, and the information input of the communication unit with the operating device, the output of which is connected to the second request output of the device, the control information input is connected to the output of the second information register command register; the first information inputs of the first, second, and third level selectors; the second information inputs of these selectors are connected to the output of the third level command information register, whose input is connected to the output of the third selector, level, output the second level selector is connected to the input of the second level command information register, the third information input of which is connected to the output of the command information register of the first level control input of the third addendum, the first information input of which is connected to the output of the pre-pump counter of the counter block, the output of the identifier of which is connected to the first information input of the selector of the first level, the output of which is connected to the input of the command information register of the first level, and the second information input - with information output of the command blocking command, output of the first

The command address selector is connected to the command address of the command drilling block and the local memory block whose input address is connected to the first input of the first command address selector, the second input is connected to the output of the counter block command address, the output instructions of the microprogram control unit are connected to the corresponding control inputs selectors of the first, second and third levels, the second selector of the address of commands, the selector of the third term, the communication unit with the operating device and the communication unit with the device PTO control memory, branching feature which output is connected to an input of feature branching unit firmware control, a write operand marker two output connected to the input operand token recording two blocks Local memory.

2, The device according to claim 1, wherein the unit Claz with the operating device contains the program mask register of the program state word and the query word register into the operating device whose output is the output of the block and the control input is connected to the control register input of the mask register and the control input of the block, the information input of the mask register is connected to the information input of the block, and the output is connected to the input of the register mask of the query word to the operational device whose absolute address input address of the block.

3, the device according to claim 1, wherein the communication unit with the memory management device contains a marker memory block, a security key register from a program state word, four AND elements, three NOT elements, three elements OR and the query word register in the memory management device, the output of which is the output of the block request, and the input of the absolute address is connected to the input of the absolute address of the block, the first gate of the first element AND, the first input of the second element AND; And the first input of the third element AND, the second which entrance is connected to vtoy input of the second AND gate, the first input of the fourth AND gate, the control input of the memory March-j

the control register input of the query word in the memory management device and the control input of the block; the input of the block address is connected to the input of the address of the marker memory block, the output of the marker of which is connected to the output of the record marker two blocks and the input of the register marker of the query word to the control unit memory whose protection input is connected to the output of the fourth element I, the second input of which is connected to the output of the protection key register from the program state word whose input is connected to the information input of the block the device of which is connected to the output of the prizes of the memory block of the markers, the output

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the third element AND is connected to the input of the first element NOT and to the first inputs of the first and second elements OR, the outputs of which are connected to the first and second code inputs of the register of the query word in the control unit, respectively. Correspondingly, the second input of the first element OR is connected to the output of the third element OR and the input of the second element NOT, the output of which is connected to. the second input of the second element OR, the output of the first element is NOT connected to the second input of the first element AND, the third input of which is connected to the output of the third element NO, whose input is connected to the output of the second element AND and the second input of the third element OR

The invention relates to the field of computer technology and is intended to work as part of a multiprocessor high-speed computers.

A central processor control device is known. With several combining levels, a command selection block, a command decoder command registers, command queue buffers, operand address buffers, a command selection control block, and an RH adder are included.

 The communication between the blocks is asynchronous, the control of the blocks is schematic. Asynchronous communications and circuit control lead to hardware complication. The instruction sampling block contains three groups of four register registers in each, which is not enough to store software cycle commands and therefore leads to a decrease in speed when executing program cycles.

The closest to the proposed technical entity is the central control unit of the digital computer system processor, which contains a command buffer, command registers of the first, second and third levels, a local memory block, operand registers, two-input adder, command counter, operand address register, block

firmware control and blocking block levels of combining, the input of the command buffer is the device input, and the output is connected to the input of the first level command register, the second to the input of the two-input adder, and the third to the input of the second level command register, the output of which is connected to the register input commands of the third level, the output of which is the output of the device, the address inputs of the local memory block are connected to the outputs of the registers of the commands of the first and third levels, the control input is connected to the output of the microprogram block pack The outputs are the inputs of the operand registers, the outputs of which are the device information outputs and connected to the inputs of a two-input adder, the output of which is connected to the input of the address register of the operands whose output is the device output, the input of the block of levels of registration is the input of the device, and the output is connected to the input. a microprocessor control unit, the outputs of which are connected to the control inputs according to the register of the address of the operands, the instruction buffer, the registers of the first, second and third levels, the registers one-.

rand, two-input adder and command counter, the output of which is the code of the QjJ device.

However, to modify the address, a two-input adder instead of a three-input adder is used, which increases the time it takes to modify the address in RX format commands (such as those received in the EC computer).

The aim of the invention is to increase the speed of the processor,

The goal is achieved by the fact that in the central control unit of the processor containing the buffering unit

commands, a local block, a counter block, a firmware control block, an address translation block, an address adder, command / registers, first, second and third level information and selectors of the first and second terms, the outputs of which are connected to the first and second the inputs of the adder address, respectively, vpsbd which is connected to the corresponding inputs of the address of the local memory block, the address translation block and the selector of the first addend, the percussion "information input of which is connected to the first information input villages the second component of the second and, with the output of the information of the base and the index of the local memory block, the first information input of which is connected to the first input of the device control information to the information input of the command buffering unit, and the second information input to the second input of the device control information the first information output of the local memory block is connected to the first output of the device’s control information, and the second information output is connected to the second output of the device’s control information, information One of the address translation block, the information input of the first addend selector, the micro-orders outputs of the microprogram control block are connected to the corresponding control inputs of the local memory block, the counter block and the command buffering block, the first and second address selector selectors, the microprogram block external requests input control unit is connected to the external device demand request, and the input of branch attributes is connected to the corresponding outputs of the branch attributes of the command buffering unit, sum Matrix of the address and the address translation block, the output of the absolute address of which is connected to the corresponding inputs of the absolute address of the local memory block and command buffering block, the outputs of the command registers of the first, second and third levels are connected to the corresponding information inputs of the firmware control block and the address inputs of the local block pa M ti, the input of the address of the command of which is connected to the input of the command of the selector of the first addend and the output of the address of the command of the block of counters, the first information whose input is connected to the output of the first-level command information register; first, second, and third level selectors are entered, the first command address selector, the second command address selector, the third term selector, the communication unit with the operating device, and the communication unit with the memory management device. the output of the request of which is connected to the first request input of the device, and the input of the address is connected to the first information input of the second selector of the address of commands and the output of the mathematics address, the third input of which is connected to the output of selec The third-party torus whose absolute address output is connected to the absolute address inputs of a communication unit with operating devices and a communication unit with a memory management device and connected to the output of the absolute address of an address translation unit, whose information input is connected to the information input of a communication unit with the memory management device, the second information input of the second command address selector and the information input of the communication unit with the operating device, the output of the TQporo is connected to the second request output of the device roystva and control information input coupled to an output of the second register command information layer, porv & 1I data inputs of the selectors the first, second. and the third level, the second information inputs of these selectors are connected to the output of the third level command information register, the input of which is connected to the output of the third level selector, the output of the third level selector is connected to the input of the second level command information register, the third information input of which is connected to the output of the register the command information of the first level and the control information input of the selector of the third term, the first information input of which is connected with the output of the preliminary signal counter The counters of the block of counters, the output of which identifier is connected to the first information input of the first level selector, the output of which is connected to the input of the first level command information register, and the second information input to the information output of the command buffering unit, the output of the first command address selector buffering commands and a local memory block whose input address is connected to the first input of the first command address selector, the second input of which is connected to the output of the command address the counter block, the micro-order outputs of the microprogram control block are connected to the corresponding control inputs of the first, second and third levels of the second command address selector, the selector of the third term of the communication block with the operating device and the memory control unit, the output of the branch sign to which connected to the input of the branch feature of the microprogram unit, and the output of the write marker of the second two is connected to the input of the record marker of the operand two blocks of the local memory. . The communication unit with the operating device contains the mask register of the program state word program and the query word register into the operation unit whose output is the block output, and the control input is connected to the control input of the mask register and the control input of the block the mask is connected to the information input of the block, and the output is connected to the mask input of the query word register in the operating device, the input of the absolute address of which is connected to the input of the absolute address of the block. A communication unit with a memory management device contains a marker memory, a security key register from a program state word, four AND elements, three NOT elements, three OR elements, and a query word register into the memory management device whose output is the request output. the block and the input of the absolute address is connected to the input of the absolute address of the block, the nerve input of the first element I, the first input of the second element I and the first input of the third element I, the second input of which is connected to the second input of the second element I, the first input And, controlled by the input of the marker memory block, the control input of the query word register to the memory management device and the control input of the block, the block address input is connected to the marker memory block input, the marker output is connected to the record marker output two blocks and the input of the marker of the query word register into the memory management device whose security input is connected to the output of the fourth element I, the second input of which is connected to the output of the protection key register from the program state word, input connected to the information input of the block, the branch output of which is connected to the code of the markers memory block, the output of the third element AND is connected to the input of the first element NOT and to the first inputs of the first and second elements OR whose outputs are connected to the first and second code inputs of the query register words into the memory management device, respectively, the second input of the first element OR is connected to the output of the third element OR and the input of the second element NOT, the output of which is connected to the second input of the second element OR, the output of the first element is NOT connected to the second input of the first element AND the third input of which is connected to the output of the third element NOT, the input of which is connected to the output of the second element AND and the second input of the third element OR. FIG. 1 is a block diagram of the central control device in FIG. a, 6 is a block diagram of a command buffering block (command buffer) i in FIG. 3 is a block diagram of the command location analysis node in the instruction buffer of the League. 4a and 6 are structural diagrams of the first and second switches of the output information of the columns of the command buffer in FIG. 5 is a block diagram block diagram of} in FIG. 6 is a block diagram of a local memory block in FIG. 7 - a collision detection node scheme for the use of the first and second operands on the League. 8 is a diagram of the first operand correction node for conLiptices (the scheme of the second operand correction node is identical in Fig. 9 is a block diagram of the processor microprogram control unit; Fig. 10 is a structured priority scheme; 11 is a block diagram of the translation unit address on Fig. 12 is a structural scheme for prefixing a real address when converting it to an absolute address in Fig. 13 is a diagram of a selector for forming a segment index and a page depending on the segment sizes and pages 1 set in the control register; Fig. 14 - block diagram of a communication unit with an operating device, Fig. 15 is a block diagram of a communication unit with a memory management device, Fig. 6 is a time diagram of the operation of the central control device for the combined execution of four commands. 1) contains a command buffering unit 1 (command buffer), the first level selector 2, the first level command information register 3, the control information can be set at the same time as the command: status word n identifier Ogrammy, command length code, signs, characteristic for the command, program and circuit error signals, comparison signals by address, etc.), second level selector 4, second level command information register 5, third level selector 6, register 7 command information of the third level, microprogram control unit 8, first command address selector 9, local memory block 10, command second selector 11, counter block 12, selectors 13-15 of the first, second and third terms, adder 16 addresses, block 17 address translation, operative communication block 18 an ion device, a communication unit 19 with a memory management device, a first control input 20 (from a memory management device), a second input 21 of control information 21 (from an operating device), a microdisk output 22, a first control information output 23 to an operating device I, the second control information output 24 / into the operating device and the device .. k .. memory management device, the second request output 25 (into the operating device), the first request output 26 (into the memory management device), outputs 27 signs branching info output output 28 command buffers, input 29 external requests, zykhods 30 identifier 31, command addresses, 32 counters pre-pumping counter, outputs 33 --35 registers of the first, second and third levels, output 36 of the first address selector comacd, output 37 of the address adder , output ZV information base and index, output 39 absolute address of the block. address translation, output 40 of the operand record record marker twoT The command buffering unit 1 (Fig. 2c, o) contains the first and second sections 41 and 42 of the command word memory (BCS) (41.1,42.1 first sections columns, 41.2, 42.2 - second section columns), the memory of command address addresses 43, the memory of 44 signs of the validity of each line of the command word memory, the memory of the 45 line interconnections, the substitution memory 46, the row address switches 47-51, the first And element 52, adder 53 address line when sampling broken (located in two adjacent words) command, adder 54 dln working the address of the memory line of the consistency when adding to it the number of the continuation column, the buffer register 55 of the connectivity for specifying the column of the memory of the connectivity in which the continuation mark is made, the buffer register 56 of the address to check the presence of the command in the memory 41 and 42 during preloading and in the write command, the switches 57 and 58 of the output information of the memory columns 91 command words, the shifter 59, the output of which; The selectable command, register 60, commands, address comparison circuit 61, etora and third AND 62 elements, switch 63 output information of communication memory columns, register 64 numbers of the column in which the command was found during its selection, NOT 65 elements to determine candidate candidate column, register 66 numbers of the continuation column, element OR 67, command analysis node 68 in sections 41 and 42, output 69 of the comparison column number, output 70 of the continuation column number, output 71 of the command format. The unit 1 for buffering instructions is intended to accumulate and preserve instructions executed by the processor according to the program in advance, and thus to reduce losses (processor time to fetch commands from the operational (buffer) memory, both during sequential execution of commands and during transmission control - Lenin. In the proposed device, a two-column variant of the command buffer is selected. The command analysis analysis node 68 in the buffer (FIG. 3) contains two comparison circuits 72, a decoder 73, four HE elements 74, four AND 75 elements and an OR element 76, output 77, corresponding to the R9-Lormat commands, output 78, corresponding to the .RX-Lormat commands. Collator 57 output of the command word memory columns (FIG. 4a) contains the element HE 79, two elements 80 for receiving information 4-7 bytes from the first section of the command buffer and the element 1 of the firmware 81. The switch 58 of the output information of the columns of the command word words (Fig. 48) contains two elements NOT 79, four elements 80 and 80 (two of them for receiving information 0-3 bytes from the second section command buffer) and the element OR 81. The block 12 counters (FIG. 5) contains a command counter 82, a selector 83, a register I4, an adder 85 for 29, 30 bits of the instruction address, a pre-pump counter 86, a counter 87 for the BST storage identifier (program state word) in the local memory, a decoder 8B, two elements NOT 89 and two elements AND 90 - (add and subtract a unit on the preload counter). The local memory block 10 (Fig. 6) of the processor contains two memories 91 and 92 (each of which has 64 lines of 8 bytes each for storing information), memory input information selectors 93 and 94, output information shifters 95 and 96 memory (O or 4 bytes left), memory output information registers 97 and 98, memory address selectors 99 and 100, memory address registers 101 and memory 102, input information selector 103, input information shifter 104, nodes 105 and 106 corrections of the second and first operands, registers 10.7 and 108 of the second and first operands, selector 109 microcommands p the first and second level of combining, the selector 110 of microcommands of three levels of combining, the selector 111 of receiving the result of the operational device, the buffer register 112, the shift code adder 113, the selector 114 of the second operand marker 115, the register 115 of operand recovery, the node 116 of conflict detection (on the use of operands ), input 117 of nodes 105 and 106 of the correction, output 118 of the selector 11 of G-microcommands, outputs 119 and 120 of the collision detection node (outputs of the correction control code of the second and first operands), information inputs of the read addresses of operands 121 and 122 collision detection nodes, output 123 of the first operand correction node 106, inputs 22.1-22.3 of the microcommands of three levels of combining. The processor's local memory block is intended for receiving, storing, modifying and issuing (in the course of executing commands with operations combined) RON, RPL values, copies of control registers (UR), copies of prefix, copies of the original ERPs (instruction state word) for each of the simultaneously executed instructions, source operands in floating point instructions with exact accuracy, source operands in decimal arithmetic commands, starting, current and ending operand addresses in format 55 commands, pa personal constants initial segment address table 15 for the tasks of the processor identifier.

1 i

The collision detection node 116 (FIG. 7) contains buffer registers.

124 addresses of operands, schemes

125 comparison of pj addresses, low address bit comparison circuit 126, eight elements AND 127

and four elements RSHI 128.

The correction unit 106 for the correction of the first operand (Fig. 8) contains three elements NOT 129 of the control code 120, eight elements AND 130 and four elements AND, PI 131.

Processor firmware block 8 (FIG. 9) contains a priority memory request request circuit 132 of a microprogram memory, a first micro-command address encoder 133, a constant memory 134, a micro-command address switch 135, a micro-command address register 136, a firmware memory 137, a register 138 microinstructions, inputs 139 requests, input 140 address constants, input 29.1 request for firmware memory, input 29.2 addresses of the first micro instructions on request. Block 8 is designed to control the operation of the processor by you (the production computer with the combination of command execution.

The priority scheme 132 (FIG. 10) .o holds eight triggers 141 (the three queries trigger and four triggers for selecting the first micro-address address), three HE 142 elements and three AND 143 elements.

The address translation block 17 (Fig. 1 contains the prefix register 144, the control register 145, the logical address register 146, the real address selector 147, the prefixing circuit 148, the segment index and page formation selector 149 depending on the dimensions set in the control register segment and page, real address register 150, register 151 of active segment table numbers, fast forwarding buffer memories 152 and 153, four comparison schemes 154, seven AND 155 elements, three NOT 156 elements, two absolute OR address elements, memory 15 8 replacing the columns of the broadcasting unit, output 27 of the branch feature upon accessing the pumping firmware of the forwarding buffer.

The address translation block 17 is for converting logs 12

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address of an operand or command in real, and then in absolute.

The prefixing circuit 148 (Fig. 12) contains two comparison circuits 159, two elements NOT 160, four elements AND 161 elements OR 162 forming an absolute address.

The segment and page index generation selector 149 (FIG. 13) contains a specific combination of segment and page size decoder 163 for controlling the selection of the page index, eight AND 164 elements (for controlling the selection of the segment index and for issuing indexes) and the index OR element 165.

The communication unit 18 with the operating device (Fig. 14) contains the program state register mask 166 of the program state word and the transfer word register 167 to the operating unit. Communication unit with an operating device. (SU) is intended to provide interaction of the processor with the operating devices on the loading of the operating device by the operation code and operands and on receipt of the operation results from the operating device.

The communication unit 19 with the memory management device (Fig. 15) contains a marker memory block 168, a protection key register 169 from the program state word, an AND 170 element, three NOT 171 elements, three OR 17 elements and a query word register 173 into the memory management device, output 27 of the branching indication along the non-integer boundary of the address of the operand. The communication unit with the memory management device (CAM) is designed to provide processor interaction with the operational (buffer) memory for the exchange of information. The exchange is initiated by transmitting from the processor to the memory management device a query word containing the number of the requested CAM (if the multiprocessor system with several CTS is considered), the absolute address of the address, the code of the operation operation (read, write, etc.) record marker, security key.

The central control unit of the processor executes commands such as those received in the EC computer. The operation of the central control unit of the processor is considered on the example of executing an .RX format command such as adding with a fixed point (Fig. 16). In the central control unit of the processor, there are 4 instruction execution levels (Fig. 16) and, accordingly, 4 alignment levels. Tacts TO, T1 - ticks of zero level, T2, TZ - ticks of the first level, the command is accepted to register 3 of the command information of the first level through the selector 2, T4, T5 - ticks. second level, on register 5 command information second level commands. is received through the selector 4. T6, T7 are third level clocks, the third level command information register 7 is received via selector 6. Typical commands of the PP, PX formats are executed in 8 cycles, the passage in succession of 4 levels. Commands that require more than 8 clocks to complete, either are at any level, more clocks, or return to the first level after the second or third level and again pass through all levels sequentially. Control of the processor in TO, T1 cycles , T2 is implemented schematically, and in TK - T7 cycles it is firmware. Census. from the level to the level produced by the firmware, under the control of the microprogram control unit 8 Let us consider the operation of the command-block COOLING unit (Fig. 2a, S) using the example of executing commands of the type received in the EC computer. Assume that the .RR format commands are executed with a length of 2 bytes,: no need to be addressed to the main stream-: m followed by operands, commands of the YA format with a length of 4 bytes and commands of the format 55 with a length of 6 bytes. Commands. are located in the main cells in command words, each 8 byte long. The sample from the main memory is produced by 8-byte words at the 24-bit address (address width 8-31), and bits 8-28 address the command spruce, and bits 29-31 (byte number) - that byte number in command word in which the high byte of the command is located. The address of the current command is generated on the Rocho of the processor counter of the processor (CrK) (8/31), and 31 is always O. The bit of the command counter (8-31) is represented as ("n + k + AND) bit and is accepted (8 -22r), k 6 (23-28r), (29-31r); Let us also assume that the selection of a command from the memory of command words (BCS) is carried out in a tact of sampling a command, and the address processing of the address of the next command in the next tact is the modification of the address. In the sampling cycle, the command, sections 41 and 42 of the command word memory (BCS) are accessed according to the address of the current command. Each row of each BCS 41 and 42 column contains an 8-byte control word. In the corresponding K-th row of the corresponding memory column of the 43 addresses, senior (8-22) addresses of the control word are written; in the corresponding rows of the memory columns of 44 signs of reality, signs of the reality of the DC are recorded (we assume that if 1, then the contents of the corresponding line BCS 41 (42) is valid and it contains the required command, if Dk 0, then the commands in the memory of the command words of the corresponding column (but this address is not). In the corresponding row of the corresponding column of the connectivity 45 is written The column number of the BCS, which is located in the continuation of this command sequence.If information is recorded in the U -and memory line 45, is not equal to zero, this means that the command continues in the BCS and is not required for analysis read () st address memory line 43 in case of a broken command.Each command line memory column consists of two sections Section 41 contains the lower 4 bytes of the control word, section 42 contains the higher 4 bytes of the control word. Referring to section 41 leads to the address from the output of the first address switch 47, referring to section 42 to the address from the output of the adder 53, which, when selecting a command, summarizes the value of the lower Ic command address bits with the value 29p of the command address. If the command address 29p is zero, then the entire command, regardless of its format, is located in the same line of the BCS buffer section 41 and 42t, and the addresses of the sections 41 and 42 are the same. If the 29p address of the command is equal to one, then the beginning of the command is located in section 41 in the Vth line at the address (.3-2ld) of the command address, and the end of the command can be located in the next (k + 1) -1 line, and therefore , will be read from section 42 at (23-28 p) + (29 p) addresses of the command. Thus, the inputs of the output switches 57 and 58 when reading a command from sections 41 and 4 receive 8 bytes of command information from each column in which a selectable command can be located. Simultaneously with reading the coherent word from the memory 41 and 42 from the memory 43 of the addresses, the 44 of the validity of the memory .45 connectivity is found at the same address of the command address {22-28p), which arrives at the address inputs of the corresponding memories through switches 48–50 addresses, respectively, the higher parts of the address of the command word, signs of reality and the number of the continuation column. In the comparison schemes, all the addresses counted from the memory 43 are compared with the older part of the Yar-22p selected command address, taking into account the fact of the elements on the elements. And the search command (beginning of it) finds c in the column in which the comparison is found. The number of the column of comparison is formed at the outputs of elements And 62. The value of the number of comparison equal to zero indicates that the required command was not found in the VCS. Similarly, the value of the continuation number equal to zero indicates that there is no continuation of this command sequence in the BCS. . By comparison, however, it is produced; switch control 57 of the output information of the lower 4 bytes of the command information, in which either the end is (if 29p of the team address is zero) or the beginning of the command (if 29p of the command address is one). If the command address 29 is zero, then the switch 58 is controlled by the compare number number 69, and the command address 29p of the command address is one, then the switch 58 is controlled by the output of the continuation column number 7716 70. The command word formed at the outputs of the switches 57 and 58 is fed to the shifter 59, where the input command word is shifted to the left by the command address code (29, ZOr), so that at the output of the shifter 59, the command is aligned with its high-order bit. The command formed in this way goes to the register of 60 commands and then from its output 2 I to the input of the selector 2 of the first level. Simultaneously with reading memory words and their memory 43 and 44, the k address is read to the same address of the k -th lines through the fourth switch 50 from memory 45. The output memory information is fed to the input of the third switch 63 output information, which is controlled by the output 69 of the comparison number. The clock information of the switch 63 is stored on the number register 66 continued 11. The comparison number of output 69 arrives at the analysis node 68 (Fig. 2a) of the command walking in the instruction buffer. The other inputs of this node receive the value 29, the address of the command and the upper two bits of the command generated at the output of the shifter 59, (output 71 of the command format). Descramble The torus 43 decodes the RR commands - “chermata (output 77) and Rx-format (all move 78). The command is considered to be found in the buffer in T1 as well, if the functions F (output 27) P (nom.comp0) Ok (29p) R4-TSHSGKSEDR) (short term / F) 1. If the node 68 of the analysis indicates the absence of a command In the memory of the command words, a procedure is performed to download the desired command word to the memory 41 and 42 of the command words from the RAM. At the same time, the corresponding entries of the address of the command word B of the memory 43 of addresses and indications of validity and continuation in memory 44 and 45 are made. Pumping of memory 41 and 42 with the new command word is possible as if the required command was not sent to the BCS, hook and in advance. The advance pumping of memory 41 and 42 is called pre-pumping (pre-pumping) and occurs at those times when the address and information paths and processor equipment are free from accessing the main memory for operands. As 5 rule. These are those moments in time when the processor executes commands of the iRR format, or moments when the processor, due to conflicts arising from the combined execution of commands, cannot start executing the next command until the command is executed. The address of the next command elephant (AKS) (8-28p) pumped in the memory 41 and 42 of command words during pre-injection is generated at the output of the address adder 16 by adding the address of the current command (8-31p) of the command counter with the value of the pre-injection counter 86 and units. When he is on the 20th roll of the ocher command word in the memory 41 and 42, the presence of this command word in the BCS is performed. For this at the address of the ACU (22-28r), which is addressed to

The memory inputs of 43 addresses, the memory 44 of the signs of reality through the switches 48 and 49 are performed to extract from the memory 43 and 44 and the analysis in the comparison circuits 61 and elements 30 and 62 of the presence of the control word in

Bks. If the command word is in the BCS, then only a note is made about the continuation in memory 45 of the connectivity in the previous one (K-O-th line 35) If no command word is found, then the older ones, tp bits of its address АКС (8-22) are stored in the memory of 43 addresses on line 39 at the address of the ACU (22-28) through the switch 48 in column 40, the number of which is defined as the number of candidates for replacement. At the same time in the same column. 44 and 45 at the same address of the ACU (22 -28) reset the validity 4S and the continuation number to zero. The number of the candidate column for replacement is The two-column buffer is defined as follows: Each time a command is selected from the k lines and 50 sections of the BCS 41 and 42, in the tact of the command, if it is found in the memory of command words, into the corresponding k-th memory line 46 the single-digit number of comparison O (if a comparison is found in the first column) or 1 (if a comparison is not detected in the first column) is recorded.

In the preload procedure in step T4, the information from the substitution memory 46 at the address of the next command word AKC (22-28) reads the information, and inverts its value determines the column number of the memory 43 - 45 and BCS sections 41 and 42 for recording in them senior bits of the address of the command word ACU, a sign of the validity of the continuation number, which is equal to zero, and the command word. Thus, the information of the column, to which there have been no calls for longer, is replaced.

The reception of the command word is kept in the T5v cycle of the command word memory at the address of the control word AKC (22-28) i entering sections 41 and 42 via the address switch 47 and the adder 53 (which at this time is adding with zero) from the output buffer register 56. At the same time, the attribute is recorded at the same address through the third address switch 49 into the memory 44 of the validity signs, and in the previous (K-1) st line of the connectivity memory 45 at the address (AKC (22-28) - 1), arriving at the input of memory TC 45 through the adder 54 and the switch 50, in the column number On the other hand, the buffer register 55 is indicated by a mark of continuation, t, e, the number of the BCS command word memory column in which the given command word is written.

On the buffer register 55, an array of memory columns 41 and 42 command words is written into which the next control word is received. Upon receipt of a subsequent state word, register 55 determines the number of the column 45 of connectivity, where it is necessary to mark the continuation

The output register comparison number 69 can also be written to the buffer register 55 if the commands are in memory 41 and 42, and there is no preloading capability, the output comparison number 69 defined in the preloading procedure or the state of the buffer register 64 that stores the comparison number control transfer commands until returning to the old branch in case of unsuccessful transition.

When executing a command to transfer control, the modified address of the command of the new branch acts as the address of the next command through the selector 9. It is performed according to

19P36

torture of sampling this regular command1 from memory 41 and 42 command words despite the fact that the result indication from the previous command has not yet been received. If this next command is in memory 41 and 42, it is necessary to execute those commands of this and subsequent commands, in which there are no irreversible actions, until the receipt of the result sign from the previous command.

In the case of an indication of a result corresponding to a successful transition, the sequence of actions to execute the commands of the new 15 branch continues and the losses to the execution of the command and control command here are minimal. In the event that the indication of the result in the previous command does not correspond to the transition, the execution of the commands of the new branch stops and returns to the commands of the old branch.

If the transition is successful, but the commands of the new branch are not in the memory of 25 41 and 42, the required command word of this new branch is pumped into the memory of 4t and 42. At the same time, in all columns of memory 45, the address (AKC ( 2.-28) -1) 30 continuation signs are reset, i.e. the connectivity of command words located adjacent in memory 41 and 42, but having different older parts of the address. owls are destroyed. The consistency of command jj words is reestablished only after the reception of the first command word from the new branch ..;

In the next step, the execution of write commands to the operative (buffer) memory Q is carried out by checking the presence of information in the memory 41 and 42 command words at the write address, res records from the output; The address translation block 17 posts the address input 39 through switches 4845 and 49 to the address inputs of the memory 43 of the addresses and memory 44 of the validity signs and then is checked in the comparison circuits 61 and AND elements 62 for the presence of command 50 words in the memory.

If at the recording address information is in memory 41 and 42, then execute the eus: micro-subprogram, mma, over which memory line 41 and 42 at this address is invalid (the signs of reality are reset in memory 44), and in all columns

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The connections of memory 45 in the preceding line are reset to continue.

It is also possible that another solution is to write the operand to the main memory and to the memory 41 and 42 simultaneously to the column in which. detected comparison. Such a solution, however, would require the presence of a selector at the information input of the memory 41 and 42 for receiving the information of the operand written to the memory.

The process of work to pre-pump commands can be carried out according to the timing diagram (Fig. 16) in conjunction with the execution. current teams. The operation of the instruction buffering unit is performed in cycles T1-T5. T1 - tact sampling team. In its first half-step, the command is read from memory 41 and 42, in the second half-step, an entry is made. T2 - the tact of address modification. If the BCS pumping procedure is completed, then the address of the control word is detected in T2, and the pre-injection counter is modified (subtracted 1) if the instruction counter during the advancement indicates a command from the next control word.

TZ- is the tact of translating the address of the command word. In this cycle, the preload counter is modified (added 1) to execute the address of the next command word. T4 is the tact of outputting information from a single (buffer) memory and checking the matrix of command buffer addresses. In the first half-cycle, reading and checking the state of the memory of 43 addresses and the memory of 44 signs of reality is conducted. If the analysis has shown that the required command word is in the memory of command words, then in the second half-cycle, only a record is kept. in memory 45, the preloading process is terminated, and the information arriving on the RAM. 211 is ignored. If the analysis showed that the required command word is not in the memory 41 and 42 of the command words, then in the second half-cycle, the addresses are stored in the memory of the 43 addresses and the bits of the validity and continuation signs (number) in the memory 44 are recorded. memory 45 connectivity. T5 is the tact of receiving the command word received from the operative (buffer) memory in memory 41 and 42. The reception is performed in the second semittate. In addition, in the second half-cycle, the continuation feature (number) is set to 1 bit of reality and in the previous memory line 45 of connectivity. The command counter 82 (FIG. 5) calculates the address of the next command based on the address of the current command and its format. The address of the current command is stored on a counter 82 (8 / 28p) and a register 84 (29, 30). The two lower order bits from register 84 arrive at the input of adder 85 as the first term. The second term is the command length (K, CC) unit arriving at input 33 of the first level command register. When calculating the address of the next command in T2, the current time. the commands, these two values add up, and the new value 29, 30 p of the address from the adder 85 through the selector 83 is written to register 84. If the result of the addition is a pair, the counter 82 receives one to the current value of 8/28 p of the address. In control transfer commands, a transition address is taken from the output of the selector 11 on the command counter. The pre-pump counter 86 is intended to provide the address of the next control word pumped into the BC relative to the command counter. The value of the pre-pump counter 86 always shows the difference in double words between the address of the command word of the current command and the address of the last command word in memory 41 and 42. If the beginning of the required command is not in the BCS, then the address of the pumped command word is equal to the value of the counter (8-28), i.e. the value of counter 86 is zero, and the addition of one is not made. Counter 86 increases (its content is equal to one each time the next command word is recorded in command memory 41, 42. One unit is subtracted from the pre-pump counter 86 once the next command is shifted to 28p when generating the address of the next command. the command counter and the command counter indicate the following control word. When the pre-pump counter 86 reaches the maximum pre-pump value (output 89 of the decoder 88), which is less than the maximum number of command words placed on one table memory memory 41, 42, further retries of preloading are suspended until the value of counters 86 decreases. This prevents / spoils information in memory 41,42 in the case of so many prefixes when BCS memory can overflow with pre-downloads, the last received command word can overwrite the string in which the next command is to be executed in the BCS. On the other hand, the value of the pre-delivery counter 86 can only decrease to zero. To limit the count to the maximum preload value and limit the subtraction to 0, a decoder 88 of these states is designed, which through the elements of NOT 89 blocks the corresponding element AND 90, from which output the signals of addition or subtraction are removed. In the initial state and in the transfer commands: control to the pre-pump counter 86: carry O, since the command words of the new branch must be pumped from the new point of reference. The counter 87 is designed to generate the identifier of the ERP, the address for storing the ERP in the local memory. It is a two-bit counter for modulo 4 instructions according to the combination levels, and for each next command it indicates its next storage location C (P in the local memory. In the initial state, it is set to O. The value of the counter 87 is set to the corresponding The control information of the first level register 3 simultaneously with the reception of command information. Then the SSP identifier moves from level to level along with all the information of this level. The local memory block (Fig. 6) perceived For buffer storage, the state of all the main processor registers and RAM information is stored, and the initial operand to the operating devices through the registers of the first AND second operands is 1 byte 8 bytes. The output of the second operand register is the main internal loading information marina of the processor through which The transfer of information to the operational memory, as well as the loading of all operational registers of the processor (SSP register, prefix register, control registers, timer block, etc.). In order to enable the simultaneous reading of two of the operands 8 bytes long, it contains two memories 91 and 92, which are independent. I. Each of the memory 91 and 92 is divided into 8 fixed zones, 8 lines of double word in each zone. Memory zones 91 are as follows: 1 is the storage area of instructions state words (soybean), which takes 4 lines to combine the commands the rest of the lines are free 2-zone storage of general purpose registers (RON), in each line of which two RON (black and odd) are stored, each 4 bytes long; - 3 - the storage area of the floating point register (RPL), in which 4 lines are stored for the storage of RPL, the remaining 4 lines are free; 4 is the storage area for copies of the control registers (ST), in each line of which two URs are stored ( even and odd) i, 5- working zone 1 for storing intermediate results, initial, final, current addresses of operands in SS-format 6 commands - working zone 2 for storing source operands in extended accuracy commands and decimal arithmetic and a copy of the prefix} 7,8-two zones for storing the processor identifier and constants, used in the process of executing commands and micro routines. The memory zones 92 can be as follows: 1 - the storage area of the original ERP of the current commands, which takes 4 lines to store the ERP, a number of commands that are executed together; 2- RON zone, which duplicates the identical zone of the memory 91; 3, zone, RIL, which duplicates the identical zone in the memory 91; 4- storage area for the initial addresses of the segment tables of several tasks. In the cd line of which is stored the information of the control registers SD (1) and SD (0) for two tasks (the code of the address of the beginning of the table of segments and the sizes of the tables of segments and pages). This zone is filled and checked each time the control load command is executed. 5-8 zones that duplicate identical memory zones 91. It is assumed that the speed of the local memory is such that there are two possible accesses to one machine cycle (cycle). The access to the local memory is made under the control of the orders generated by each command in the first half of the tacts T1, T2, TK ,, and the microcommands of the first, second and third levels of combination in the first or second half of the tact, and the number of the half-tact is specified in the microinstruction itself. Vlok 10 of the local memory works as follows. At the beginning of the sampling of each command in the first half-cycle of the T1 cycle, the current MTP is recorded at input 36 through the selector 94 in memory 92 at an address equal to the storage identifier of the ERP in the local memory received from output 30 the block of the block-: command ticker through the selector 100 to the address register 102. When moving the command code ng, the next level of combination with it also moves the code of this identifier. With each successive command, the identifier of the ERP at the zero level is not increased by 1J the score is organized modulo the number of levels of combination 251

nor, in this case, modulo four.

Thus, for four commands executed simultaneously on four levels of combining, it ensures that their initial MSPs are kept in the local memory, the storage address of the MSP (identifier) in the MSP zone is known and stored at the appropriate level for each command.

In the next T2 cycle, the address modification cycle, the values of the index and the base are read from the local memory in the first half cycle. The address of the index from the RON zone indicated in the command field of the first level of combining is fed to the register 101 of the memory address 91 through the selector 99 through. input 33, and the address of the base (from the POI zone), also indicated in the command field of the first combination level, goes to the register 102 of the address of memory 92 via the selector 100 to the input 33. At the same time, it sets the address of the POH zone. The read values of the index and the base go to the output registers.

97 and 98 through selectors 95 and 96. If the low-order bit of the index or base address is 1, which indicates an odd RON, then selectors 97 or.

98, the corresponding left-by-four bytes is produced, so the index and base are always located in output registers 97 and 98, aligned (left from the left position. Index and base values arrive at output lines 38 to the inputs of the address adder 16 processor through selectors 13 and 14.

In the next step of translation of the address of the TZ, the word of the state of the instruction (FID) is also memorized at inputs 31 and 37 through the selector 93 in memory 9

The storage address of the current FID in the FID zone is equal to the storage address of the BSC in the BSC zone of this command and is taken from the BSC ID floor at the first level of aliasing. It enters the register 101 memory address 91 through the selector 99 at input 33.

Preserving the current FID in local memory allows the firmware to run at any time. To access its contents at the identifier address at the appropriate level. This is necessary, for example, when executing control transfer commands, when

7726

to return to the old branch, an advanced command counter value is required when interrupts when it is not possible to memorize the old MSP in commands that use the modified address not as the operand address, but as the operand (shift code, channel and subscriber number, etc.). n.) in control recovery procedures where the value of the address of an operand corrupted in the RAM is used, and so on.

All the specified actions in cycles T1, T2, TZ are executed in the first half-cycle under the control of the orders issued in each command, regardless of the command code.

In the next processor cycle, cycle T4, in its second half-cycle, the initial first operand is read in the RX-Lormat commands, or the first and second operands in the RR-L-command commands, under the control of the second-level microcommand on registers 97 and 98.

Depending on the command code, the readout from the RON, RSHR, or SD zone is sent to the addresses of the operands indicated in the corresponding field of the second-level combining command. Accordingly, the address of the first operand enters the register 102 of the address of memory 92 via the selector 100, the address of the second operand (in RR-format commands) enters the register 101 of the memory address 91 through the selector 99. The values of the operands are read into the output registers 97 and 98 through selectors 95 and 96. If odd numbers of RON or SD are indicated, then the corresponding left shift is made by 4 bytes. In case j if the operands are long (8 bytes), or if the number of the even RON or SD is indicated, the reading is performed without shifting, i.e. can be counted immediately two EPR (UR), the even and the odd01, located in one line of the local memory.

In the next clock cycle T5, registers 107 and 108 are loaded into the operating device through registers 107 and 108 of the second and first operands.

The registers 107 and 108 are loaded under the control of the microcommand of the second level of combining;

271

register 98 through the node. 106 of the correction (Fig. 7) is entered into the register 108, and the second operand comes from the output of register 97. through the selector 103, the shifter 104 (without shifting), the correction unit 105 to the input of the register 107. reading the operand, whose modification in the previous command has not yet been completed.

This analysis is performed by the collision detection node 116 (Fig. 6) by comparing the read addresses of the operands stored in the buffer registers 124 with the result record address in the previous command from the output 35 of the third-level register 7. The length of the recorded result (along line 118) and the parity of the RON number (RPL) of the result and the read operands are taken into account.

The detection of conflict is performed independently of each operand in two separate circuits. As a result of conflict detection, the corresponding trap1 control code of nodes 105 and 106 of the frustration of operands through which the unchanged parts of registers 107 and 108 are transferred to the unchangeable parts of registers 107 and 108, and the variable parts of registers 107.and 108; the corresponding parts of the result worked out in the previous team are received.

In the case of an RX command; -format the second operand nociynaer from one of the operative (buffer) memory at input 20 through selector 103, shifter 104, node 105 of correction to register input 107. At the same time, at shifter 104, the left byte number is shifted operand), so that the operand is differentiated by its left-hand bit. The shift code is generated by the shift adder 113, not one input of which receives the byte number, to the second input a shift constant. The shift constant is specified in the yux instruction and is used when executing load commands for half words, symbols, and, if necessary, to form the operand by shifting. The shift is circular and can be set from 0 to 7 bytes. The same shifter 104 is also used when reading the operand from

or through the selector SW of receiving any other information in the write commands to the operational (buffer) memory. In this case, the shift code is also generated on the adder 113, but the byte number is subtracted, i.e. the shift is done by byte number to the right. Information is received by register 107 by a marker received through a selector 114. The marker is eight-bit and the unit in the marker's size permits the change of the corresponding byte of register 107, and zero keeps the value of this byte as before.

The reception marker on register 107 is either explicitly specified in the microcommand (input 1 of the selector 114), or read from the memory of the marker constants (input 40 of the selector 114), which is accessed at an address composed of a three-digit byte number code and a three-digit length code the operand specified in the microinstruction.

The combination of the work of the shifter 104 and the marker makes it possible to form operands from parts of various sources, as well as to form an operand in the case of its noninteger boundary, i.e. when it is located in two adjacent cells of the operative (buffer) memory.

At the third level of combining, in the step T6, the contents of the register 107 of the second operand are received through the selector 111 to the buffer register 112 of the result in the load instructions RON, RPL, SD. In addition, in this clock cycle, the contents of the variable operand (first or second) to the operand recovery register 115 are received. The output of register 115 is fed to the input of selector 103, and in the procedures for restoring an operand to monitor its contents, it can restore the corrupted RON or RPL operand in the local memory.

In the last cycle of command execution, the result recording cycle T7, the result of the operating device received through the selector 111 to the buffer register 112, goes through the selectors 93 and 94 to the information inputs of memories 91 and 92 and is written to the corresponding zone (RON or PL) address of the first operand specified in the command field of the third level (input 35). The recording is performed by the control of the third level microcommand in the BTopQM semi-cycle. Recording to both memories is carried out according to the record marker in the local memory specified in the third level microcommand, and the information is shifted to the right by 4 bytes in the Tori villages 93 and 94, if the result is written in odd ron. When executing the commands of 65 Lormat, it is necessary to shift some intermediate results by 1 or several bytes. These actions are performed under the control of micro-commands, in which the intermediate result is read from the working area, at the address explicitly specified in the micro-command, to register 97 in the first semitact, shift it by shifting 104 by the required number of bytes and write again to the working area by the same or another address in memory 91 and 92 in the second half-cycle of the same machine cycle. The introduction of separate selectors 9 and 94 for memory 9t and 92 makes it possible to use more optimally the entire amount of memory at the expense of non-duplicate areas for storing the ERP, DFI, initial addresses of the segment tables. Thus, the possibility of local memory in a high-performance processor with n levels of combining is achieved by building control and selecting addresses from n () various levels of combining with sharing the time to access local memory in p-half-tacts for micro instructions, simultaneously . By the number of combining performed by the firmware, the memory 134 of constants, the register of 136 addresses of microinstructions, the memory 137 of the microprogram and the register of 138 microcommands in block 8 of the microprogram control (Fig. 8) are divided into sections. In the case of the proposed central control unit of the processor of such sections 3. The inputs 33–35 from the registers 3, 5 and 7 of the command information of the first, second and third levels receive operation codes of the commands being executed. On the encoder 133, the addresses of the first micro-command, provided that there is a command in the video conferencing system (input 27), the constant of the first micro-command is generated by the operation code of the command on the first level. (If the BCS required for executing a command into the buffer is not detected, then the address constant of the first microcommand of the command word pumping procedure is exceeded on the pcfraser 133). The address constant of the first micro-command enters the switch 1.35 of the micro-instructions, then into the register of 136 addresses of the micro-commands. By. This address is used to fetch the first microcommand from the memory 137 of the microprograms. The first micro-instruction is placed on the register 138 micro-instructions. The address of the next microcommand is generated in the address switch 135, the microprogram memory section 137 number, branch conditions contained in the microcommand word and evaluating the corresponding branching symptoms at the output 27 of the address constants entering the micro commands command 135 and constants memory 134. The signs of branching at output 27 are generated in process blocks when executing NIC micro-commands and can affect the generation of the address of the next micro-command, if indicated in the micro-command. In addition to processing the commands, the firmware control unit 8 processes console, timer operations, interrupts, and recovery recovery procedures for monitoring. Requests for the processing of these procedures are received at input 29.1.in priority scheme 132. The address constants of the procedures, which set the fixed addresses of the first micro-commands of the microprograms for processing these procedures, arrive at a given 140 in the switch 135 addresses of the micro-instructions. Further processing of procedures is carried out in the same way as the execution of commands. The memory 134 of constants stores not only address constants, but also other data necessary for executing instructions (e.g., a sign of the privilege of the instructions being executed, the lengths of the operands, etc.). The constants and micro-orders go to the central control unit of the processor via outputs 22. A two-section memory 152, 153 of the fast forwarding buffer (BPL) of the address translation unit (Fig. 9) serves for storage and operational

3111361

using the strings of the most frequently used page table. Buffer 152, 153 of the fast forwarding is organized as a cache memory (caa / p). An address-associative method is used for searching information in the fast forwarding buffer. Circuitry leads immediately to both columns 152, 153 through the lower 6 bits (15/20) of the analyzed logical page address, coming from register 146 of the logical address. The value of the gender of the highest bits of the logical address (8/14) of the register 146 of the logical address is compared in the second 15 fourth schemes 154 compared with the value of the field read from both columns 152, 153. If the values of these fields are found to be equal in one of the 20 columns, this means that the required row of the page table is in the fast redirection buffer and is written in the real address field of the column where this 25 equality is detected.

Buffer 152, 153 fast forwarding foryt stores ablitz lines from many tasks at the same time, as for each task there may be a separate redirection table and how many parameters are the sizes of pages and segments). For this purpose, in memory x 152 and 153, there is a storage field for the identifier of the segment table. On . Register 151 of the active segment table number stores the identifier of the segment table that is active at a given moment.

Every time when the fast forwarding buffer is accessed, the segment identifier field is read simultaneously with the logical address, the value of which is compared Neither the first and the third comparison schemes 154 j with the value of the register 151 of the active table number of segments. The equality of logical addresses found in the second and fourth comparison schemes 154 is taken into account when the segment identifier field and the active segment table number fall together.

The active number of the segment table in register 151 is set every 55 times when executing a load of control register 145 that stores the start address of the segment table 32

77

com, page size and segment. The content of this control register 145 is stored in a special zone 4 of the local storage unit 10 at the address, which is its ideifier.

If, when accessing the buffer 152, 153, the required page table row is not found, then the branch on the 155 .27 element formed on AND 155 will be searched for the required rows of the segment tables and pages into the operative memory and pump the redirect buffer.

The procedure for pumping the redirection buffer is as follows.

The address of entry into the segment table is calculated on address adder 16. The first addend through the selector 13 posts on input 38 the value of the address of the beginning of the segment tables counted from the control register area of the local memory unit 10, the second addend receives zero and the third addend through the selector 15 comes from the output of the selector.

149segment index value. Calculated real line address

table segments at the input 37 is supplied through the selector 147 to the register

150 real address and after prefixing in the scheme 148 through the elements And 15 Ifflli 157 enters the block 19 generating the query word in the UE.

The contents of the segment table row are the real address of the beginning of the page table. To form the entry address into the page table, the first addend receives a zero, the second addend through the selector 14 through input 24 contains the contents of the second operand register, the third addend through the selector 15 receives the page index from the output of the selector 149. Issuing the address of the page table to the request block 19 The memory management device is conducted in the same way as the segment table address. I

Required page table row

from register 107 operand two at input 24 goes to selector 147, and then to register 150 of the real address.

The real, res (8/19) bits are subjected to prefixing on the prefixing circuit 148, and then the fast forwarding line and section 152 33 and 153 of the fast forwarding are placed at the same time as bits 8-14 of the logical address from the register output 146 in the field of the logical address and at the same time with the register value 151 of the active number of the segments in the number field of the segment. The selection of a column for entering information in the procedure for pumping the redirect buffer is the same as selecting a column when replacing command words in the buffer. In the replacement memory 158 in the T2 translation clock, the addresses are stored in the column number in which the address comparison is detected. In the pumping procedure for inverting the contents of this memory, the column number to which you need to record information is determined. To the register 167 of the query word, in block 18, the communication is t-operative. The device (Fig. 14) in step T5 enters the operation code at input 34 from the register 5 second-level commands, the shift code (the lower six bits of the modified address from register 150) from the output 39 of the block 17) program mask from the register 166 of the program mask. In addition, register code 167 can be entered by the SU type code (positionally) by the microinstruction code if the pacc failsafe device is used in a multiprocessor system with several OU types that share common resources for several processors. In the latter case, the result information of each OU type to the processor on input 21 via a selector (not shown in FIG. 1) under the control of block 18. In the communication unit with the memory management device (FIG. 15), the query word is generated on register 173. Absolute address is received at input 39, a. also 20 p The size of the logical address and the size of the page to form the number of PMU. If the device in question is used in a multiprocessor system with several CAMs, then information from each DSP, issued on request from the processor, must be received at input 20 through a selector (not shown in Fig. 1) under control of block 19. After markers at input 37 of The address adder 16 receives three lower-order bits of the logical address (byte number of information transmitted), micro-orders and a constant specifying the length of the operand to be written to the memory are received at input 22. A marker field read from the memory of 168 markers is written to the request word register 173 to the memory management device. Register 169 holds the security key of the program state word. Under the control of micro-orders 22, this key is stored on the query word register 173 into the memory management device. From the micro-orders 22, the operation code of the memory management device is generated, which is written to the register 173. To the query word in the device. Memory codes also include the number of the memory management device, since the proposed central control device of the processor can be used as part of a multiprocessor. Room . control devices pa. The memory is generated by the elements 170 - 172 based on the bit (20) of the logical address, the bit (20) of absolute adhesion, the size of the page arriving at the input 39 from the address translation unit and the instructions controlling the generation of the memory management device number. The generated memory management device block is written to register 173. The generated request word is output to memory management device on output 26. In addition, the second operand receive control marker is sent to local memory block 10 on output 40 107, and in block 8 of the firmware control, output 27 indicates a branching indication in the case of a non-integer boundary operand (i.e., when the operand is located in two adjacent memory cells). The proposed invention provides a significant advantage in speed as compared to the known one by using the three-way address adder 16 to modify the address, which allows all modifications to be made not in two cycles, as in the known device, but in one, the presence of buffer 1 of high-capacity command words ( 128 g of words), which allows you to store several program words in the buffer of command words.

351136

cycles, as well as due to the presence of a selector 9, which allows you to quickly generate the address of the control transfer command to search for this command in block b

In the known device in the case of

successful transition is spent eight cycles, and in case of unsuccessful transition of five,

The processor speed increase was also achieved due to the introduction of a one rand correction circuit into the device in case of an operand conflict determination due to overlapping operations. Saving in the local memory ts COPY of the original operands, BSC, prefix. The control of the register allows you to repeat the commands in which: an error occurred. Besides.

36

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By introducing an internal data bank of the local memory, the structure of the processor is ordered, its functionality is increased by executing various tests and diagnostic procedures, and the register equipment is reduced to build a number of control and working registers. The introduction of non-duplicated local memory zones improves the optimal use of memory, which also reduces the equipment to build the corresponding buffer registers (tables of the beginning addresses of the segments, the value of the modified addresses of the operands, and the command counter).

The overall gain in speed is 31% D%.

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Claims (3)

1. The CPU CENTRAL CONTROL DEVICE, comprising a command buffering unit, a local memory unit, a counter unit, a firmware control unit, an address translation unit, an address adder, command information registers of the first, second and third levels and selectors of the first and second terms, the outputs of which are connected to the first and second inputs of the address adder, respectively, the output of which is connected to the corresponding inputs of the address of the local memory block, address translation unit and selector of the first term, the first whose irrational input is connected to the first information input of the second term selector and to the output of the base information and the local memory block index, the first information input of which is connected to the first input of the control information of the device and the information input of the command buffering unit, and the second information input is to the second input of control information device ^1, the first information output of the local storage unit connected to the first output of the control device information and the second information output - to the WTO the output control information of the device, the information input of the address translation unit, the information input of the selector of the first term, the microproducts of the microprogram control unit are connected to the corresponding control inputs of the local memory unit, the counter unit and the command buffering unit, the selectors of the first and second terms and the address translation unit, input external requests of the microprogram control unit is connected to the input of external requests of the device, and the input of branching signs to the corresponding and outputs of indications of branching of the command buffering unit, address adder and address translation unit, the output of whose absolute address is connected to the corresponding inputs of the absolute address of the local memory unit and the command buffering unit, the outputs of the command information registers of the first, second and third levels are connected with the corresponding information inputs of the microprogram unit there is a lot of control and address inputs of the local memory, the input of which address is connected to the input of the selector command of the first term and you Odom block instruction address counters ^ first information vkod coupled to an output of the first register command information urs SU „, .1136177 nya, characterized in that, in order to improve performance, the first, second and third levels selectors, the first command address selector, the second command address selector, the third term selector, the communication unit with the operating device and the communication unit are introduced into it with a memory management device, the request output of which is connected to the first request input of the device, and the input address is the first information input of the second command address selector and the output of the address adder, the third input of which is connected to the output of the third selector of the term, the input of the absolute address of which is connected to the inputs of the absolute address of the communication unit with the Operating device and the communication unit with the memory management device and is connected to the output / absolute address. address translation unit, the information input of which is connected to the information input of the communication unit with the memory control device, the second information input of the second command address selector, and the information input of the communication unit with the operating device, the output of which is connected to the second request output of the device, and the control information input is connected to the output of the register of command information of the second urban nov, the first information inputs, selectors of the first, second and third * levels, the second information inputs of these villages Ktorov connected to the output of the third level command information register, whose input is connected to the output of the third selector. level, the output of the second level selector is connected to the input of the second level command information register, the third information input of which is connected to the output of the first level command information register and the input of the control information of the third term selector, the first information input of which is connected to the output of the preliminary pump counter of the counter block, identifier output which is connected to the first information input of the first level selector, the output of which is connected to the input of the command information register of the first level two, and the second information input - with the information output of the command buffering unit, the output of the first command address selector is connected to the command address inputs of the command buffering unit and the local memory block, whose address input is connected to the first input of the first command address selector, the second input of which is connected to by the output of the address of the command of the counter block, the micro-control outputs of the microprogram control block are connected to the corresponding control inputs of the selectors of the first, second and third Levels, the second selector the addresses of the commands, the selector of the third term, the communication unit with the operating device and the communication unit with the memory control device ¹ , the output of the branch sign of which is connected to the input of the branch sign of the microprogram control unit, and the output of the operand write marker two is connected to the operand write marker input two local memory blocks . 2, device pop. 1, characterized in that the communication unit with the operating device contains a program mask register of the program status word and a query word register in the operating device, the output of which is the output of the unit, and the control input is connected to the control input of the mask register and the control input of the unit, the information input of the mask register connected to the information input of the block, and the output to the input of the mask of the query word register in the operating unit, the input of the absolute address of which is ✓ connected to the input of the absolute address of the block. 3. The device according to π. 1, characterized in that the communication unit with the memory management device comprises a marker memory block, a security key register from the 'status word' of the program, four AND elements, three 'NOT elements, three OR elements and re: query word histories to the memory management device whose output is the output of the block request, and the input of the absolute address is connected to the input of the absolute address of the block, the first input of the first AND element, the first input of the second AND element and the first input of the third AND element, whose second input is connected to the second input of the second electronic ment And, the first input of the fourth element And, the control input of the memory block markers, controlling the input of the query word register to the memory control device and the control input of the block, the input of the address of the block is connected to the input of the address of the marker memory block, the marker output of which is connected to the marker output write two blocks and the input of the register marker of the query word into the memory control device, the security input of which is connected to the output of the fourth element And, the second input_ of which is connected to the output of the security key register from the word with the melting of the program, the input of which is connected to the information input of the block, the branching of which is connected to the output of the signs of the marker memory block, the output of the third AND element is connected to the input of the first element NOT and to the first inputs of the first and second OR elements, the outputs of which are connected to the first and second to the code inputs of the query word register in the memory management device, respectively, the second input of the first OR element is connected to the output of the third OR element and the input of the second element NOT, the output of which is connected to the second Odom second OR gate, the output of the first element is coupled to the second input of the first AND gate, the third input of which is connected to the output of the third NOT element whose input is connected with output of the second AND gate and a second input of the third OR gate,