SU1117715A1 - Storage with checking and correcting errors - Google Patents

Abstract

1. STORAGE DEVICE C. CONTROL AND CORRECTION OF ERRORS, containing a register of numbers and drives, each of which contains the main storage elements located at the intersection of the main address and bit buses, additional memory elements located on the additional address and bit buses, the decoder strings whose outputs are connected to address buses, a selector, an absolute modulo two, a sampling signal generator and a column decoder, the outputs of which are connected to one of the selector inputs, others The e inputs of which are connected to the main bit buses and one of the inputs of the modulo adder, the other inputs of which are connected respectively to the additional bit bus and to the output of the sampling signal generator and the control input of the selector, the outputs of which are the outputs of the accumulator, and the output of the adder modulo-two is a control terminal of the accumulator, the inputs of the row decoders and column decoders of all the drives are respectively combined and are the device's address inputs, the inputs leu sampling signals are one of the actuating device inputs of tlichayuschees in that, for the purpose povsh1eni. accuracy of control, a group of adders modulo two, blocks of control sum, a group of elements OR, groups of majority elements, a control unit and the first element § OR are entered into the device, the first group of inputs of each modulo two are connected to the same outputs of the accumulators, and the output is connected to the first inputs of the same majoritarian elements of the groups and the same input. the first element OR, one of the inputs of each check sum block is connected to the outputs of the same name accumulator, and one of the number register inputs, the other inputs of which are connected to the outputs of the major elements of the groups, one of the inputs of each element OR group are connected to the outputs of the same name block of the check sum and the other input is connected to the control output of the accumulator of the same name and the second inputs of the majority elements of the group of the same name, the third inputs of which are connected to the output of the same name The modulator is modulo two of the second group, the first input of which is connected to the control output of the same name accumulator, and the second input to the output of the same name of the NIII group.

Description

One of the inputs of the control unit is connected to the outputs of the OR elements of the group, and the other inputs are connected respectively to the output of the first OR element and to the inputs of the sampling drivers, control inputs of the number register are connected to one of the outputs of the control unit, the other outputs of which and the number register outputs are respectively the control and information outputs of the device, the other inputs of the check sum blocks are respectively combined and are other control inputs of the device.

2. The device according to claim 1, characterized in that the control unit contains the second element OR, the elements AND, the element OR NOT, the element NOT the driver of single pulses, the delay element, the decoder of the error signals, whose inputs are one of the inputs of the block, one of the outputs is connected to the first input of the first element AND, and the other outputs are connected to the inputs of the second element OR, the output of which is connected to the first inputs of the OR-NOT element and the second element AND, the second input of which is connected to the input of the element NOT, the output of which is connected to the second in One of the first element is And, the output of KOTOpofo is connected to the second input of the element OR NOT, the output of which is connected to the first input of the third element And, the output of the second element And is connected to the first input of the fourth element And, the second inputs of the third and fourth elements And are connected to the output of the delay element The input of which is connected to the output of the single pulse generator, the input of which and the input of the element are NOT other inputs of the block, the outputs of the single pulse generator and the delay element are one of the outputs of the block, you the moves of which are the outputs of the third and fourth elements I.

one

The invention relates to computing, in particular, to storage devices, and can be used in discrete information processing systems that have high demands on reliability.

A memory with error control and correction is known, consisting of separate, well-defined multi-bit memory modules, and it uses a code that allows the error packet lj to be corrected.

The disadvantage of this device is the large information redundancy and the impossibility of detecting two or more error packets.

Closest to the invention is a memory device with control and error correction, containing drives consisting of. main rows and columns of storage elements, an additional row and an additional column, an address decoder, a modulo two,

selector, number register, storage register of checksum, group of keys, correction prohibition trigger, two-bit counter, AND elements, ELEVENESS DENIAL, the first counter output is connected to one of the inputs of the first And element, the other input of which is connected to the output of the modulo modulator two, and the output is connected to one of the inputs of the keys of the second group and to the input of the counter, the outputs of the accumulator are connected to the corresponding inputs of the adder, pi module two, the number register and the first inputs of the elements EQUALITY DENIAL, out The numbers of the register of numbers are connected to the first inputs of the keys of the first group, the other inputs of which are connected to the output of the 2j address decoder. The disadvantages of the known device are the inability to correct errors caused by failures on more than one line, even the multiplicity of errors, the need to stop the operation of the device even in the case of a single error, which reduces the accuracy of the control. - The aim of the invention is to improve the accuracy of the control of the storage device. This goal is achieved by the fact that in a storage device with a monitor and error correction, contains a register of numbers and drives, each of which contains the main aaphomi elements, located at the intersection of the main address and different buses, additional memory elements located on the auxiliary address and the discharge bus is a row decoder, the outputs of which are connected to the address buses, a selector, an absolute modulo two, a for- maker, a sampler of signals, and a decoder of the columns, the outputs of which are connected to one from the selector inputs, the other inputs of which are connected to the main bit buses and one of the inputs of the modulo two, the other inputs of which are connected respectively to the additional bit bus of the output of the sampling signal generator and the control input of the selector, the outputs of which are accumulator outputs bodies, and the output of the modulo-two adder is the control output of the accumulator, and the inputs of the row decoder and decoder columns of all the drives are respectively combined and are address inputs TVs, the inputs of the sampling signal conditioners are one of the control inputs of the device, modulo-two adder groups are entered, check summing units, the OR element group, the major element groups, the control unit and the first OR element, and the modulator the first two groups are connected to the same outputs of accumulators, and the output is connected to the first: the inputs of the same majority elements of the groups and the same input of the first OR element, one of the inputs of each control block is summed up connected to outputs of the accumulator of the same name and one of the inputs of the register, the other inputs of which are connected to the outputs of the majority of elements of groups. one of the inputs of each element OR group is connected to the outputs of the same sum block of the control sum, and the other input is connected to the control output of the same name accumulator and the second inputs of the majority elements of the same name group, the third inputs of which are connected to the output of the same adder modulo two second groups, the first input of which connected to the control output of the storage device of the same name, and the second input - to the output of the element of the same name OR group, one of the inputs of the control unit is connected to the outputs of the elements OR g groups and other inputs are connected respectively to the output of the first OR element and to the inputs of the samplers, the control inputs of the number register are connected to one of the outputs of the control unit, the other outputs of which and the number register outputs are respectively the control and information outputs of the device, the other inputs of the check sum blocks, respectively, are combined and are other control inputs of the device. I In addition, the control unit contains the second OR element, the AND elements, the OR-NOT element, the NO element, the single pulse shaper, the delay element, the error signal decoder, whose inputs are one of the block inputs, one of the outputs is connected to the first input of the first element AND, and other outputs are connected to the inputs of the second element OR, the output of which is connected to the first inputs of the element OR NOT and the second element AND, the second input of which is connected to the input of the element NOT, the output of which is connected to the second input of the first element AND, output which is connected to the second input of the element OR NOT, the output of which is connected to the first input of the third element AND, the output of the second element AND is connected to the first input of the fourth element AND, the second inputs of the third and fourth element TRV And are connected to the output of the delay element whose input connected to the output of a single pulse generator, the input of which and the input of the element are NOT other inputs of the block, the outputs of the single pulse generator, and the delay element. are one of the outputs of the unit, the other outputs of which are the outputs of the third and fourth elements I. Figure 1 shows the functional diagram of the proposed device, fig. 2 and 3, respectively, are functional diagrams of the most preferred options for terminating the control unit and each check totaling unit. The proposed device contains (figure 1) register 1 numbers, drives 2, each of which contains the main address 3 and bit 4 buses, additional address 5 and bit 6 tires, a decoder for 7 lines, a decoder for 8 columns, a selector 9, a driver 10 signals sampling and adder 11 modulo two. At fig, address 12 and 13 and one of the control 14 inputs are designated. The device also contains the first element OR 15, the first group of adders, 16 modulo two, the control unit 17, the control summation blocks 18, the second group of elements OR 19, the second group modulo two adders 20, the majority element group 21. FIG. 1 also denotes inputs 22 and 23 of register 1, inputs 24–26 of control unit 17, other control inputs 27 and 28 of the device, outputs 29 and 30 of control unit 17, control inputs 31 and 32 of register 1, control 33 and information 34 outputs of the device. The control unit G7 contains (FIG. 2) a second OR element 35, AND 36-39 elements one through four, an OR element NO.40, a HE element 41, a single pulse former 42, a delay element 43, and an error signal decoder 44. Each check sum block 18 contains (fig.Z triggers 45 and AND 46 elements with inputs 47. The device operates as follows., The device carries out operational hardware control of the read information using a three-dimensional iterative code, with parity of the read information for each from the coordinates, namely, the parity control of rows and columns of each drive 2 and the parity check of the same-named bits 11 of all drives 2. For this, when writing information to the device, the additional values Each element in each row is formed as a sum modulo two values of the main storage elements, and the values of additional storage elements of a column are formed as a sum modulo two values of the main storage elements. From all drives 2, one is the control of each word as a sum of two values like bits of the remaining (information) drives 2. The operation of block 17 is carried out as follows. Upon admission to the inputs of 24 zero code at the input level 25 log. Oh and the input 26 signal-. A sample of one of the drives 2 at the first output of the decoder 44 (FIG. 2) appears at the log level. 1, and on the remaining outputs - the level of the log. 0. At that, the output of the element AND 36 will set the level of the log, 1, and the output of the element OR 35 will be set to the level of the log, 0. Accordingly, the outputs of the element Р1ПИ-НЕ 40 and the element And 37 form the levels of the log. 0. On the leading edge of the sampling signal, the shapers 42 are triggered, the output of which generates a pulse signal of a certain duration, which arrives at the output of block 17 and through the delay element 43 (the value of which is determined by the maximum response time of elements 44, 35, 40 and 37 or 44, 36 and 40) is fed to the inputs of the elements And 38 and 39. At the same time, the outputs of the elements 38 and 39 establish the levels of the log. 0. If a code containing one unit is input to inputs 24 and a log level is input to input 25, one of the outputs of the decoder 44 will be excited, which are connected to the inputs of the OR element 35, the output of which will be set to log level, 1, and at the output of the AND 36 element, the level of the log, O will be set, while the outputs of the elements of the 38 and 39 will also set the level of the log, 0. If the input containing the code containing one unit and the input of 25 the level of the log, 1, then the output the element And 38 will set the level of the log O, and the output of the element 39 and the level of the log. If a code containing more than one unit arrives at inputs 24, then regardless of the level at input 25 at the output of the And 38 element, the level of log 1 will be set; and at the output of the element And 39 level log.0. If the zero code is set at the inputs 24, and the log.1 level is at the input 25, then the output of the And 38 element will set the level of the log, 1 and the output of the And 39 level will change the log. 0. The signal from the output 29 to the input 31 resets the register 1 (Fig. 1) to the zero state, and the signal from the output 30 receives the information in the register 1. The information signals arrive at the inputs 23, and inputs 22 correction signals. In the presence of level LOG.1 at the input 22, the signal arriving at the input 23 of the corresponding bit is inverted, i.e. It is being repaired. By the signal arriving at input 28, the blocks 18 are set to the zero state. In the presence of a raresting level Log.1 at the input 27, the signals arriving at the inputs 47 (FIG. 3) are fed to the counting input of the corresponding trigger 45, on which modulo two are read in addition to two reads from the drives 2. When reading information before starting work, input 28 sends a reset signal for blocks 18 to the zero state. At inputs 12 and 13, an address code of the readable number is set, an input signal is output to input 14, according to which information is allowed to be retrieved from accumulators 2 and shaper 42 is triggered on the leading edge, with a signal from which register 1 is set to zero the number set at input 12 selects one of the lines of accumulator 2, and according to the code of the number set at input 13, a part of the selected line is selected and through selector 9 is transferred to the output of accumulator 2. In the absence of errors in readings IOM word at the outputs of adders 11 and 16, are set levels log. 0. At the same time, at the outputs of all elements OR 19, the levels of the log are set. Oh, and the outputs of the C5 4matorov 20 levels log. 1 and. Accordingly, at the outputs of the majority elements 21, an internal log.O. At the inputs 24 of the block 17, the 5V code is set to zero, and the log.O. level arrives at the input 25 from the OR 15 element. After the transients are established from the delay element 43, the read word signal is received in register 1. Since the correction signals at the outputs of all major elements 21 correspond to the level of the log O, the code of the number without correction read from the accumulators 2 is set to register 1, while output: t 33 block 17 set the code 00, indicating the absence of errors in the read word. When a single or any odd number of errors occur in the read line, the output of the adder 11 corresponding to the faulty accumulator 2 appears at the level nor.i which enters the inputs of the corresponding elements OR 19, the adders 20 and the majority elements 21, at the outputs of which accordingly the level of LOG.1 and the levels of the log.O. In this case, if there are no errors in the read part of the string, then the output of all the adders 16 are set to the levels of the log file. O. In this case, only one of the inputs of the majority elements 21, corresponding to the faulty drive 2, is set to levels of LOG.1 and, therefore, their outputs set the level of the log.O. The inputs 24 of block 17 receive a code containing one unit, and the input 25 receives a log level. 0. At the same time, code 00 is set at outputs 33, indicating that there is no error in the read word. If there are errors in the read word, then at the outputs of adders 1b corresponding to the faulty bits, levels of LOG 1 are set, which are fed to the same major elements 21 corresponding to the faulty drive 2, the second inputs of log 1 are received, while Correction signals corresponding to the level of LOG 1 appear on their outputs. As a result, the errors are corrected, and code 01 is set to the outputs 33, indicating. the presence of correctable errors in the readable word. If an even error occurs in the read line, it is not detected by adder 11, but is detected by adders 16. In this

In the case of outputs 33, code 10 appears, indicating the occurrence of an unrecoverable error. The operation of the device is stopped at the input 27, a level of log.1 is set, which allows receiving information in blocks 18, and the accumulator 2 is monitored by columns. If errors are detected only in one of the drives 2, then the operation of the device can be continued. In this case, for lines containing even the number of errors, the symptom of malfunction occurs from block 18 corresponding to defective drive 2, and for lines with an odd number of errors from the output of adder 11. Such separation of signs is provided with adders 20. In the event of signs of error more than one drive 2, at outputs 33 it is set

code 10, indicating a fatal error.

Thus, the proposed device allows to correct all single and any number of odd errors occurring in each row of drive 2, packet errors caused by the failure of one of drive 2, detect two or more error packets, diagnose the storage device with memory chip accuracy. without interrupting the operation of the device, disconnect and remove the failed storage device from the device 2.

The technical and economic advantage of the device proposed is a higher accuracy of control as compared with the known device.

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Claims (2)

1. MEMORY DEVICE C. CONTROL AND CORRECTION OF ERRORS, containing the register of numbers and drives, each of which contains the main memory elements located at the intersection of the main address and bit buses, additional memory elements located on the additional address and bit buses, a line decoder, the outputs of which are connected to the address to buses, a selector, an adder modulo two, a shaper of sampling signals and a decoder of columns, the outputs of which are connected to one of the inputs of the selector, the other inputs of which are connected to the main there are two modular output buses and one of the inputs of the adder, the other inputs of which are connected respectively to the additional discharge bus and to the output of the sampler and is controlled by the control output of the drive, and the inputs of row decoders and column decoders of all drives are respectively combined and are address inputs devices, the inputs of the drivers of the sampling signals are one of the control inputs of the device, characterized in that, in order to increase, the accuracy of control, in the device introduced in adders modulo two groups, control of summation units, a group of elements OR, groups of majority elements, a control unit and the first element OR, with the inputs of each adder modulo two of the first group connected to the drive outputs of the same name, and the output connected to the first inputs of the group items of the same name and the input of the same name. q of the first OR element, one of the inputs of each control summation block is connected to the outputs of the drive of the same name, and one of the inputs of the number register, the other inputs of which are connected to the outputs of the majority elements of the groups, one of the inputs of each element of the OR group is connected to the outputs block of the same name checksumming, and the other input is connected to the control output of the drive of the same name and the second inputs of the majority elements of the same group, the third inputs of which are connected to the output of the same name a second modulo two groups (Turvey input of which is connected to the input selector mu whose outputs are the outputs of the drive, and the output of the modulo two adder output yavlyaupravlyayuschemu same name of the storage ring and the second input - to the output of the OR group of the same name> one of the inputs of the control unit is connected to the outputs of the OR elements of the group, and the other inputs are connected respectively to the output of the first OR element and to the inputs of the shapers of the sampling signals, the control inputs of the number register are connected to one of the outputs of the control unit, the other outputs of which and the outputs of the number register are respectively control and information outputs of the device, other inputs of the checksum blocks are respectively combined and are other control inputs of the device. 2. The device according to claim 1, characterized in that the control unit contains a second OR element, AND elements, an OR-HE element, an element NOT a single pulse shaper, a delay element, a signal decoder · errors whose inputs are one of the inputs of the block, one of the outputs is connected to the first input of the first AND element, and the other outputs are connected to the inputs of the second OR element, the output of which is connected to the first inputs of the OR-HE element and the second AND element, the second input of which is connected to the input of the NOT element, the output of which is connected to second input the first element And, the output of which is connected to the second input of the OR-HE element, the output of which is connected to the first input of the third element And, the output of the second element And is connected to the first input of the fourth element And, the second inputs of the third and fourth elements And are connected to the output of the delay element, whose input is connected to the output of the single pulse shaper, the input of which and the input of the element are NOT the other inputs of the block, the outputs of the single pulse generator and the element from the outputs of the third type I. whose output delays are one block, others are the outputs of the fourth element