SU1117670A1 - Device for recording power conditions - Google Patents

Abstract

1. DEVICE FOR REGISTRATION OF OPERATING MODES OF THE ENGINE, containing sensors, analog-digital converter, switches, synchronization unit, memory unit, the output of which is connected to the first input of the information output unit, elements And register, characterized in that, in order to increase accuracy devices, analog-digital converters and digital signal level analyzers, blocks of OR elements, OR element, adder and decoder, the first output of which is connected to the first inputs of digital analyzers, are entered into it Signal level and analog-to-digital converters, to the second inputs of which the first output of the synchronization unit is connected, the sensor outputs are connected to the third inputs of the corresponding analog-digital converters, the outputs of which are connected to the third inputs of the corresponding digital signal level analyzers, the outputs of which are through the first block of OR elements connected to the inputs of switches, the outputs of which are connected to the first inputs of the second block of OR elements, the output of which is connected to the first input of the memory block, output which through the adder is connected to the first inputs of the elements. And, the outputs of which are connected to the first input of the register, the output of which is connected to the second input of the memory unit, to the third input of which the second output of the decoder is connected, the third output of which is connected to the second inputs of the AND elements, the first output of the information output unit is connected to the first input of the OR element the output of which is connected to the fourth input of the memory block, the fourth and fifth outputs of the decoder are connected to the second inputs of the OR element and the register, respectively, the second output of the information output unit is connected to the second inputs the second block of OR elements, the second output of the synchronization block is connected to the input of the decoder and to the control inputs of the switches. 2. A device according to claim 1, characterized in that the synchronization synchronization unit comprises a switch, a frequency divider, a counter and a pulse generator, the output of which is connected to the first input of the switch, the first output of which is connected to the first input of the frequency divider and is the first output of the synchronization unit The total power supply is connected to the second input of the switch, the second output of which is connected to the first input of the counter and to the second input of the frequency divider, the output of which is connected to the second input of the counter, the output of which is the second output output of the sync block.

Description

3. The device according to claim 1, of tl and h and y. It is that the digital signal level analyzer contains an element AND, a comparison element, an encoder, a decoder and a counter, the output of which is connected through the serially connected decoder and encoder to the first input of the comparison element, the second input of which is the third input of the digital analyzer

the signal level, the first input of which is the first inputs of the counter and the element And whose output is connected to the second input of the counter, the output of the comparison element is connected to the second input of the element AND, the third input of which is the second input of the digital signal level analyzer, the output of the decoder is output digital signal level analyzer.

The invention relates to the field of registering the operating modes of machines with variable parameters and can be used, for example, for multichannel registration and obtaining statistical information about the multiparameter mutual distribution of the operating modes of an internal combustion engine over time during testing and operation of its ground transport maps. A device for metering the engine operating time during operation and testing it in ground transport vehicles is known, which includes sensors of measured parameters, which are frequency sensors of speed and load modes, connected through converters in the form of pulse counters and decoders to a memory unit, representing the block of time counters L. However, this device does not provide multi-channel registration and acquisition of statistical information on the multiparameter mutual distribution of engine operating modes in time. The closest to the invention to the technical essence is a device for registering engine operation modes, containing sensors analog-digital converter, switches, synchronization unit, memory block, the output of which is connected to the First input of the information output unit, elements AND, register, comparators , control unit and amplifiers 2j. The known device does not provide statistical information about the mutual distribution of engine operating modes over time during testing and its operation on land transport vehicles due to the recording of information in separate memory cells for each level of each measured parameter. In this connection, allowing to solve private and independent tasks on research of modes, this device cannot be used to solve the main task - to determine the distribution of modes depending on each other, and consequently, to determine the actual engine load when operating it in a transport machine in conditions of unsteady motion patterns. . The aim of the invention is to improve the accuracy of the device by providing multi-channel registration and creeping statistical information about the multiparameter mutual distribution of engine operating modes over time. The goal is achieved by the fact that a device for recording engine operation modes containing sensors, an analog-to-digital converter, switches, a synchronization unit, a memory unit whose output is connected to the first input of the information output unit, And elements and a register, are inserted -digital converters and by the number of sensors digital signal level analyzers, blocks of elements OR, element OR, adder and decoder, the first output of which is connected to the first inputs of 31 digital signal level analyzers and analog-tsref transducers, to the second inputs of which the first output of the synchronization unit is connected, the sensor outputs are connected to the third inputs of the corresponding analog-digital converters, the outputs of which are connected to the third inputs of the corresponding digital signal level analyzers, the outputs of which through the first block of OR elements are connected to the switch inputs, outputs which are connected to the first inputs of the second block of OR elements, the output of which is connected to the first input of the memory block, the output of which through the adder is connected to The first inputs of the elements And, the outputs of which are connected to the first input of the register, the output of which is connected to the second input of the memory block, with the third input of which is connected the second output of the decoder, the third output of which is connected to the second inputs of the elements And, the first output of the information output unit connected to the first input of the OR element, the output of which is connected to the fourth input of the memory unit, the fourth and fifth outputs of the decoder are connected to the second inputs of the OR element and the register, the second output of the output unit n to the second inputs of the second block of OR elements, the second output of the synchronization block is connected to the input of the decoder and to the control inputs of the switches. The synchronization unit contains a switch, a frequency divider, a counter and a pulse generator, the output of which is connected to the first input of the switch, the first output of which is connected to the first input of the frequency divider and is the first output of the synchronization unit, the common power supply is connected to the second input of the switch, the second output of which is connected to the first input of the counter and to the second input of the frequency divider, the output of which is combined with the second input of the counter, the output of which is the second output of the synchronization unit. In addition, the digital signal level analyzer contains an element And, a comparison element, an encoder, a decoder and a counter, the output of which is connected through the serially connected decoder and encoder 70 to the first input of the reference element, the second input of which is the third input of the digital signal level analyzer, the first input which are the first inputs of the counter and the element And, the output of which is connected to the second input of the counter, the output of the comparison element is connected to the second input of the element And, the third input; which is the second input of the digital signal level analyzer, the decoder output is the output of the digital signal level analyzer. FIG. 1 shows a block diagram of the proposed device; in fig. 2 is a block diagram of an implementation of a digital signal level analyzer. The device contains a sensor 1,. analog-digital converters 2, digital signal level analyzers 3, first block 4 OR elements, switches 5, second block 6 OR elements, memory block 7, adder 8, AND elements 9, register 10, information output block 11, OR element 12 , generator 13 pulses, switch 14, frequency divider 15, counter 16, decoder 17, tires 18 and 19, synchronization unit 20. . The digital signal level analyzer 3 contains a comparison element 21, an AND element 22, an encoder 23, a decoder 24 and a counter 25. The input signals, for example, the signals of the frequency sensors of the speed and load modes and the signal of the potentiometric brake sensor, form one of the groups of measurements parameters. Other groups can be formed by signals from sensors of transmission number, thermo, vibration, strain gauges, acceleration sensors, fuel supply sensors, etc. The device works as follows. The signals from sensors 1 of the measured parameters are fed to the inputs of analog-to-digital converters 2, converting the analog signal in the code working in the time interval specified by the synchronization unit 20 through the decoder 17, the commands of which cyclically, in a certain sequence with a given polling interval of recording and recording, for example 5 in this case, polling and recording 1c, the parameters C of the transducer outputs are measured; 2 signals in digital form are sent to the analyzers of the 3rd V15 level. Using the counter 25, the decoder 24 and the encoder 23, the level boundaries in the digital code are set, which is compared to the output element 21 of the converter 2. Before the codes start, the element 22 is locked with the signal of the decoder 17. After the parameter At the output of the converter 2, a code is set corresponding to the measured parameter, and is fed to the comparison element 2, on the other hand, the code corresponding to the first-level face enters it. At the beginning of the process of determining the level boundary of the measured parameter, the And 22 element may either appear to be first or open. If the value of the measured parameter, expressed in the code, is less than the code corresponding to the first boundary, the element AND 22 remains locked, the generator pulses 13 do not arrive at the counter 25, and the decoder 24 remains in the first state corresponding to the first level. If the value of the measured parameter, expressed in a code, is greater than the code corresponding to the first boundary, the element AND 22 is unlocked, and the generator pulses 13 begin to go to the counter 25, which changes its state until the level boundary code is set, corresponding to the value of the measured parameter. As a result, the element AND 22 is locked and the flow of the generator pulses 13 to the counter 25 is stopped. To the input block. 4, a single code is received corresponding to the states of the decoder 24, i.e. The levels of the measured parameter, which is converted in block 4 into a binary code, which is a part of the address code of the used memory cell. The complete combination of the address code is formed by all the OR elements of block 4 constituting this group, and by the command of the decoder 17 through the switches 5 channels and blocks .6 enters the address inputs of the memory block 7. Simultaneously with the signal 706 of the counter 16, switching switches 5, from the decoder 17 to the control inputs of block 7, the signals are written - read directly and signals are selected by the chip through the OR element 12, and the Enter and Reset signals are sent to the And 9 elements and the register 10 respectively . According to the decoder 17 read and select chips, the contents of the memory cell, the address of which is currently set on the address inputs of block 7, are fed to the information inputs of the adder 8, from which output the cell contents are increased, increased by one, since the sequential transfer input The indication of the addition of a low-order unit is established. At the command Entry, the elements of AND 9 and the contents of the adder 8 are entered into register 10. P. According to the Record and Select Chip commands, the contents of register 10 are entered back into memory block 7 in the same cell. After the above operations are executed by the signal, the reset register 10 is reset, and the output of the decoder 17 generates another signal, at the command of which, with the help of switch 5, the following inputs of block 4 are connected to the address inputs of block 7. cell memory is repeated. The reading of information accumulated in the memory cells is carried out by moving the switch 14 to the position Reading from the Write position and with the receipt of a command to read from the outside. Upon enrolment . signals from the outside, for example from the performer, in block 11, the code of the address of the memory cells is generated, coming in through block 6 to the address inputs of block 7, and at the same time a signal is selected chip select, coming to its control input through the OR element 12. By these signals the information accumulated in the memory cells is brought to the external medium, such as punched tape, by means of block 11. The read rate is set by an external recorder, such as a tape punch. Memory block 7 contains 512 memory cells with a capacity of 16 bits each. One of the groups of recorded parameters is, for example, the parameters of the speed, load and brake modes. For a predetermined range of measured rotational speeds of the speed range shaft within the range of 0-108 Hz, ten levels with uneven division steps are set. For a given range of measured frequencies of rotation of the shaft of the load mode within 50-91.7 Hz, eight levels with uneven division steps are established. For the specified range of the measured DC voltage of the brake mode sensor within 0–24 V, four levels are set with a step of 6 V. 320 memory cells are allocated for this group of parmeters. The remaining ki are distributed among other groups or individual parameters. 08 The proposed device for recording the vehicle's operating modes over time, in contrast to the known mode, allows for multi-channel registration and obtaining statistical information about the multi-parameter mutual distribution of engine operating modes over time and then DISCHARGING information, for example, using a tape punch on a computer that provides a more complete and rapid refinement of the engine load modes in the engine and, allows to justify the choice of More stressful modes for carrying out strength calculations and to specify the program of long bench tests of the engine, which will ultimately improve the reliability, efficiency and durability of the transport engine.

K 20

KZ

FIG. Z

Claims (3)

1. DEVICE FOR REGISTRATION OF ENGINE OPERATING MODES, comprising sensors, an analog-to-digital converter, switches, a synchronization unit, a memory unit, the output of which is connected to the first input of the information output unit, AND elements and a register, characterized in that, in order to increase the accuracy of the device , it introduced analog-to-digital converters and, according to the number of sensors, digital signal level analyzers, blocks of OR elements, an OR element, adder and decoder, the first output of which is connected to the first inputs of digital analyzers of the signal and analog-to-digital converters, to the second inputs of which the first output of the synchronization unit is connected, the outputs of the sensors are connected to the third inputs of the corresponding analog-digital converters, the outputs of which are connected to the third inputs of the corresponding digital signal level analyzers, the outputs of which are connected through the first block of OR elements with the inputs of the switches, the outputs of which are connected to the first inputs of the second block of OR elements, the output of which is connected to the first input of the memory block, the output of which is through ummator connected to first inputs of elements. And, the outputs of which are connected to the first input of the register, the output of which is connected to the second input of the memory unit, the second output of which is connected to the second output of the decoder, the third output of which is connected to the second inputs of AND elements, the first output of the information output unit is connected to the first input of the OR element, the output of which is connected to the fourth input of the memory unit, the fourth and fifth outputs of the decoder are connected to the second _β inputs respectively of the element (In that OR and register, the second output of the information output unit is connected to the second inputs of the second of the first OR block, the second output of the synchronization block is connected to the decoder input and to the control inputs of the switches. 2. The device according to p. 1, characterized in that the synchronization unit comprises a switch, a frequency divider, a counter and a pulse generator, the output of which is connected to the first input of the switch, the first output of which is connected to the first input of the frequency divider and is the first output of the synchronization block, common the power bus is connected to the second input of the switch, the second output of which is connected to the first input of the counter and to the second input of the frequency divider, the output of which is connected to the second input of the counter, the output of which is the second output m sync block. SU .... 1117670 3. The device according to π. 1, characterized in that the digital signal level analyzer contains an AND element, a comparison element, an encoder, a decoder and a counter, the output of which is connected through a series-connected decoder and encoder to the first input of the comparison element, the second input of which is the third input of the digital signal level analyzer, the first the input of which is the first inputs of the counter and the And element, the output of which is connected to the second input of the counter, the output of the comparison element is connected to the second input of the And element, the third input of which is With the second input of the digital signal level analyzer, the decoder output is the output of the digital signal level analyzer.