SU1086419A1 - Function generator - Google Patents

Abstract

A FUNCTIONAL GENERATOR containing a functional conversion unit, a control unit, a result counter and an integral counter, which has an eMi. that, in order to increase reliability, it contains a memory block and an address counter, and the control block contains a delay element, an And element and a trigger whose ilkhod is connected to the first input of the And element, the second input of which is connected to the input of the clock pulses of the generator and the input of the functional block transformation, the output of which is connected to the input of the address counter and the installation input to 1 trigger, the installation input to O which is connected to the output of the interval counter and through the delay element to the read input of the memory unit, the address input and the output of which is connected respectively to the output of the address counter and the installation input of the interval counter, the counting input and output of which are connected respectively to the output of the element I and the input of the result counter, the output of which is connected to the output of the generator.

Description

The invention relates to computational tools of control systems and measurement systems and can be used to reproduce a function with the values of a code specified at discrete points in time, in the spaces between these moments, and as a control unit of a specialized device, which is occupied with processing of continuous processes. A device containing a counter and a memory block is known, the counter outputs are connected respectively to the address inputs of the memory block.} In this device, clock by clock through the address code received from the counter output, the code of the fuzzuonal dependence is read from the memory block. A disadvantage of the known device is a large amount of equipment. So, for example, when playing an exponent with an argument width of eleven bits and a 1024-1 chip capacity, the device contains about 190 packages. The closest in technical terms to the offer is a function generator, containing first and second counters, a control unit, and a functional conversion unit. , the subtraction and summation schemes and the SHSh t2 element. The disadvantage of the known generator is the complexity of the control unit design, it must store information about all approximations and, after analyzing the input code, issue commands to control various units and using different frequencies. The purpose of the invention is to increase the hope of the generator. I The goal is achieved by the fact that the function generator, which contains the function conversion unit, the control unit, the result counter, and the terval counter, contains a memory block and an account. An address block, the control unit contains a delay element, an element and a trigger, the output of which is connected to the first input of the element I, the second input of which is connected to the input of the clock | 1x generator pulses and the input of the functional conversion unit whose output is connected to the input of the address counter and the input settings in 1 trigger, the installation input in O of which is connected to the output of the interval counter and, through a delay element, to the read input of the memory unit whose address input and output are connected respectively to the output of the address counter and the installation input of the interval counter., the counting input and the output of which are connected respectively to the output of the element And and the input of the result counter, the output of which is connected to the output of the generator. The drawing shows the block diagram of the generator. The functional conversion unit can be executed according to the scheme of any device that plays a partial-pulse-dependency, for example (.3. The functional generator contains the functional transformation unit I, the counter 2 addresses, the memory block 3, the interval counter 4, the result counter 5, block 6 control, delay element 7, element 8 I, trigger 9 and 10 of block 1. The proposed function generator works in the following way. At the start of operation, the value of the correction interval for the first pulse is entered into the counter 4, o to 10 functional conversion unit 1. Each pulse from output 10 generates an address C in counter 2 and turns on trigger 9 of control block 6. Correction of the number from memory block 3 transmits counter 4, in which an impulse delay correction from output 10 to the desired interval (in cycles). An overflow pulse from the dynamic output of counter A is fed to counter 5 to form the final result. Each time after the completion of the correction cycle, a pulse from the dynamic output of counter 4 through delay element 7 is fed to the input of block 3 the memory and serves as a command to read from the memory block 3 and write to the counter 4 an additional code of the value of the next correction interval. The clock pulses arrive at the input of the functional conversion unit 1, as well as through the element 8 I to the counter 4, the output of which is scanned to update the correction information.

3 10864194

In this generator, the number of the younger part — the correction issue is reduced to the number of function jumps, in memory block 3, has a small

and the duration of the intervals between the jump-number of bits.

Kami is divided into two components: chapters-Thus, an increased part is achieved by the block 15 reliability as a result of

function-to-conversion, avani — one frequency frequency.

Claims (1)

FUNCTIONAL GENERATOR, comprising a functional conversion unit, a control unit, shafts, characterized by TeMj. that, in order to increase reliability, it contains a memory unit and an address counter, and the control unit contains a delay element, an element And a trigger, the output of which is connected to the first input of the element And, the second input of which is connected to the input of the clock pulses of the generator and the input of the functional conversion unit the output of which is connected to the input of the address counter and the input of the setting to 1 trigger, the input of setting 0 to which is connected to the output of the interval counter and through the delay element to the read input of the memory block, the address input and output for which are connected, respectively, with the output of the address counter and the installation input of the interval counter, the counting input and output of which are connected respectively to the output of the And element and the input of the result counter, the output of which is connected to the output _ni , 1086419