SU1078604A1 - Pulse repetition frequency doubler - Google Patents

Abstract

A PULSE FREQUENCY DIGITAL, containing a pulse generator, summing and calculating pulse counters, an OR element whose first input is connected to an input bus and a reset input of a pulse adding counter, characterized in that, in order to simplify the device, the output of the pulse generator is connected to counting inputs summing and subtracting pulse counters, the enable input of the recording of the subtracting pulse counter is connected to the input bus, the output of the 1st bit of the summing pulse counter is connected to information by the 1–1st digit output input of the subtracting pulse counter, where 1, ..., h G The loan and the output of the impulse counter subtracting counter are connected to the second O) input of the OR element. with

Description

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o :) The invention relates to a pulse technique and can be used in discrete measurement systems. The following frequency doubler is known, containing a pulse generator, the output of which is connected to the first inputs of the first and second And elements and the third and fourth directly through a frequency divider, the second inputs of the First and Four elements And are connected to the input bus through an inverter, and the second and third , the outputs of the first reversible pulse counter are connected through the first decoder to the first input of the OR element and the third input of the first AND element, and the outputs of the second reverse pulse counter are Ina through the second decoder with the second input of the OR element and the third input of the second element AND, the first and second inputs of the first pulse counter are connected to the outputs of the first and third elements AND, respectively, and the second input of the second and fourth elements AND, respectively. lies in its complexity and large range of elements included in it. The closest in technical essence to the proposed invention is a pulse frequency frequency doubler, which contains an impulse generator, a summing pulse counter whose reset input is connected to the first input of the element — OR, a reversible (summing and subtracting) pulse counter / outputs of which are connected to the first group the inputs of the code comparison element, the second group of inputs of which is connected to the outputs of the summing pulse counter, and the output with the second input of the OR element and the first input of the trigger, the second input of which is connected is connected with the input bus and direct and inverse inputs with the first inputs of the first and second And elements, respectively, the second inputs of which are connected via a frequency divider to the output of the pulse generator and the first input of the third element And, the second input of which is connected to the right trigger house and the output is connected to the first input of the reversible pulse counter, the second input of which is connected to the output of the first element I, and the account input of the cyrc 1 pulse counter is connected to the output of the second element I h. The disadvantage of this device lies in its complexity. The purpose of the invention is to simplify the frequency adjuster. The goal is achieved by the fact that a frequency pulse doubler contains a pulse generator, summing and subtracting pulse counters, an OR element whose first input is connected to the input bus and the reset input of a pulse adding counter, the pulse generator output It is connected to the counting inputs of the summing and subtracting pulse counters, the enable input of the recording of the subtractive pulse counter is connected to the input bus, the output of the 1st digit of the summing counting counter Pulse ik is connected by a synformational input of the (i-l) -ro discharge of the deductive pulse counter, where 1 l, ..., li, and the output of the subtractive pulse counter is connected to the second input of the OR element. The drawing shows a block diagram of the proposed pulse frequency doubler. The device contains a pulse generator 1, summing and subtracting counters 2 and 3. pulses and an OR 4 element, the first input of which and the reset input of the summing counter 2 are connected to the input bus 5 of the device and the write enable input of the subtractive counter 3, the second input of the OR 4 element is connected to the output of the 3rd subtractive counter 3, and the output is you one bus 6 of the device, the output of generator 1 is connected to the counting inputs of summing and subtracting counters 2 and 3, and the output. - the bit of the summing counter 2 is connected to the information input (1-1) of the th bit of the deducting counter 3. The device operates as follows. After the input pulse arrives, the contents of counter 2 are rewritten into counter 3 on the leading edge, then counter 2 is rolled over the trailing edge of this pulse. Record from the output of the th digit of counter 2 is carried out in (1-1) -th digit of counter 3. In this case, the number recorded in counter 3 will be two times less than the number in counter 2. This is true if the number in the counter 2 even. Otherwise, an error occurs that is inversely proportional to the frequency ratio of the generator 1 and the input signal. As the pulses of the generator 1 arrive at the counting input of the counter 2, its contents increase, and the contents of the counter 3, the subtraction of the input of which is also connected to the generator 1, decreases. At the moment of zeroing of the counter 3, an impulse appears at its output, which passes through the OR 4 element to the bus b. Because

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the number stored in the counter 3 in order to ensure the correct

Two times less impulses. functioning device selection

owls generated for the period of the input frequency of the pulse generator and the emitted signal, i.e. the contents of the count-bone of the summing counter of the impulse 2 at the end of the period, then the pulses (based on the minimum frequency

at the output of the counter 3 borrowing of the input signal (3)

bathe in the middle of the gap and eliminate the overflow between the adjacent input pulse of the pulse counter,

mi (the first impulse may turn out in this way, the proposed yct is not in the middle of the gap, which is known from the initial content, and is dependent on the initial content for the same frequency of the generator 3) from the pulse frequency is two times less.

Claims (1)

A PULSE FREQUENCY FREQUENCY DOUBLER, comprising a pulse generator, summing AND subtracting pulse counters, an OR element, the first input of which is connected to the input bus and the reset input of the summing pulse counter, characterized in that, in order to simplify the device, the pulse generator output is connected to the counting inputs of the summing and subtracting pulse counters, the recording permission input of the subtracting pulse counter is connected to the input bus, the output of the ί-th discharge of the summing pulse counter is connected to the information the output of the ϊ -1st digit of the subtracting pulse counter, where <= 1, ..., And the output of the `` Loan ¹ 'of the subtracting pulse counter is connected to the second input of the OR element.