SU1076952A1 - Storage with self-check - Google Patents

Abstract

A SELF-MONITORING STORAGE DEVICE containing a memory block whose address input is connected to the first output of the address register, the information input of the memory block is connected to the first output of the information register, and to the first input of the element block I, the output of the memory block is connected to the first input of the information register, the second input of which is connected to the first output of the first block of adders modulo two, the third input of the register of information is connected to the first input of the first block of adders modulo two and to the first output of the first buf A serial register whose outputs are informational inputs of the device, the second output of the first buffer register is connected to the second input of the first block of modulo-two adders, the second output of which is connected to the first input of the error register, the second input of the error register is connected to the output of the first convolution unit, the first and the second inputs of which are connected respectively to the second and third outputs of the address register, the second output of the information register is connected to the first input of the comparison unit, the second input of which is connected to n The first output of the second block of adders modulo two, the input of the second block of adders modulo two is connected to the third output of the data register, the fourth input of which is connected to the first output of the second buffer register, the second output of the second block of modulators two is connected to the second input of the I block, the third input of which is connected to the output of the first decoder, the first output of the comparison unit is connected to the input of the first decoder, to the input of the second decoder and to the input of the syndrome analysis unit, the first output is It is connected to the counter input, failures, the output of the second decoder is connected to the fourth input of the AND block whose output is connected to the input of the second buffer register, the second output of the second buffer register is connected to the input of the second convolution unit and is the information output of the device, the second output of the block analysis of syndromes is connected to the third input of the error register, even (the late input of which is connected to the output of the second convolution unit, the output of the error register is connected to the input of the OR element, whose output is controlled The output output of the device, the inputs of the first buffer register are informational BxojlliMH devices, characterized in that, in order to improve speed, it contains four registers, two triggers, a selection unit and a display unit, the first and second inputs of which are connected to the outputs of the first and second triggers, respectively, the third input of the block (SINDIND is connected to the output of the first register, the first input of which is connected to the first input of the second, third and fourth registers, to the first inputs of the first and second trigs the second inputs of the first and second triggers are connected to the corresponding outputs of the selection unit, the first and second inputs of which are connected respectively to the output of the first decoder and to the first output of the information register, the fourth input of the display unit is connected to the output of the second register, The second entrance is connected to the third you.

Description

The address register register, the fifth input of the display unit is connected to the output of the quarter-register, the second input of which is connected to the FiTopOM) output of the comparison unit, iuecToA

The comparison unit input is connected to the output of the third register, the second input of which is connected to the third output of the comparison unit.

The invention relates to the construction of monitoring and diagnostic devices and can be used in specialized and universal computers. A device for controlling memory I is known. A disadvantage of this device is that it does not provide the possibility of localizing faults in parallel with computer tasks. A device for collecting erroneous information in memory 2 is known. The disadvantages of the device are the high costs of equipment (an additional storage device has been introduced) and the time loss associated with fixing the state of the memory registers for any error. Closest to the present is a self-monitoring memory device that allows for the correction of information in the event of failures that distort one digit in a word. And in the event of failures that lead to the distortion of two or more bits, the known device allows the memory device to remember the state of the memory registers for the next analysis. A disadvantage of the known device is that in the event of faults that lead to the distortion of information in one bit, the state of the memory registers is not preserved to ensure the localization of the fault location. Therefore, the localization of such faults cannot be carried out in parallel with the solution of the problem, which leads to a decrease in the speed of the memory device and a decrease in the coefficient of technical use of computers. The purpose of the invention is to increase the speed of the device. The goal is achieved by the fact that in a self-monitoring memory device containing a memory block whose address input is connected to the first output of the address register, the information input of the memory block is connected to the first output of the information register and to the first input of the I block of elements, the output of the memory block connected to 11p | -) input of the information register, the second input of KOTOf) OrO is connected to the first output of the first block of modulo-two adders, the third input of the information register is connected to the first input of the first block of modulo-adders a and the first output of the first buffer register, whose inputs are the information inputs of the device, the second output of the first buffer register is connected to the second input of the first modulo-two block, the second output of which is connected to the first input of the error register, the second input of the error register is connected to the output the first convolution block, the first and second inputs of which are connected to the second and third, respectively) outputs, the address register, the second output of the information register is connected to the first input of the comparison block, the second the input of which is connected to the first output of the second block of adders modulo two, the input of the second block of adders modulo two is connected to the third output of the information register, the fourth input of which is connected to the first output of the second buffer register, the second output of the second block of modulators two is connected to the second input And, the third input of which is connected to the output of the first decoder, the first output of the comparison unit is connected to the input of the first decoder, to the input of the second decoder and to the input of the syndrome analysis unit mov, the first output of which is connected to the input of the fault counter, the output of the second decoder is connected to the fourth input of the I block; the output of which is connected to the input of the second buffer register, the second output of the second buffer register is connected to the input of the second convolution unit and is the information output of the device , the second output of the syndromes analyzer is connected to the third input of the error register, the fourth input of which is connected to the output of the second convolution unit, the output of the error register is connected to the input of the OR element, the output of the cat The device is a controllable ush. device output, the inputs of the first buffer register are information inputs of the device, add; 1b 1o four registers, two flip-flops, a selection unit and a display unit are entered, the first and second inputs of which are connected to the first exit and second triggers. the third input of the display unit is connected to the output of the first register, the first input of which is connected to the first input of the second, third and fourth registers, to the first inputs of the first and second triggers and to the first output of the syndrome analysis unit, the second inputs of the first and second triggers are connected to the corresponding outputs of the block selection, the first and second inputs of which are connected respectively to the output of the first decoder and to the first output of the information register, the fourth input of the display unit is connected to the output of the second register, the second the input of which is connected to the third output of the address register, five inputs of the display unit are connected to the output of the fourth register, the second input of which is connected to the second output of the comparison unit, the sixth input of the comparison unit is connected to the output of the third register . FIG. 1 shows a block diagram of the proposed device; in fig. Figures 2 and 3 show the functional diagrams of the syndrome analysis unit and the display unit. The device contains inputs 1-3, address register 4, information register 5, buffer registers 6 and 7, modular two modulators 8 and 9, comparison block 10, moduli 11 and 12, modulo two convolutions, AND unit 13, decoders 14 and 15, a register of 16 errors, an OR element 17, a syndrome analysis block 18, a failure counter 19, outputs 20 and 21, a memory block 22, registers 23-26, triggers 27 and 28, a selection block 29 and an indication block 30. Input 1 to the device is a two-wire line through which the "Write, Read" signals, which determine the operation mode of the memory block 22, are received. Input 2 to the device is a line through which an address code is transmitted with check bits. The control is organized by byte. Input 3 to the device is a 72-wire line. Input 3 receives information, each byte of which is accompanied by one check bit. Register 4 addresses is built on O-triggers and serves to store the address that needs to be addressed to the RAM block. Register 5 of information is used to store information when writing to the RAM and after reading. In addition to the 64 information bits, it contains eight bits of the correction code. Built on D-triggers. The buffer register 6 is used to store information to be written to the RAM. In addition, the 64 information bits contain eight test bits, one for every eight bits of information. Built on triggers. Buffer register 7 is used to store information read from operative memory. It contains 64 information bits, eight control bits and eight bits of the correction code. Built on D-triggers. Module 8 of modulo-two adders ensures that 1 information is correctly received at the first buffer register 6, and also generates corrective code bits in accordance with the Hayming code. The inputs of block 8 receive information and check bits from the outputs of the buffer register 6. The first output of block 8 is the correction code generated for the entire 64-bit information word. It is connected to the input of register 5 information. The second output of block 8 represents the outputs of eight convolutions, each of which collapses eight information bits and one corresponding control one, coming from the outputs of register 6. The second output goes to the first input of the 16 error register. Block 8 is implemented on modulo two add-on circuits, for example, 500 IE 60. Block 9 modulo-two adders are used to form the 64-bit information code of the Hamming code (first output) and eight test bits on incoming 64 input bits. for modulo control two (second exit). Block 9 is implemented, for example, in integrated circuits 500 of IE 60. Block 10 of the comparison is used to form the syndrome code. It consists of eight comparison circuits, each of which receives the bit of the correction code from the output of the information register 5 and from the output of the block 9 modulo-two adders. Block 11 of the modulo two convolutions serves to verify the correctness of the reception of the address code to the address register 4. Implemented on 500 IE 60. Block 12 of the modulo two convolutions serves to control the correctness of receiving information on the buffer register 7. Implemented on 500 IE 60. Block 13 of the I elements serves to transfer 7 bits of information, control and correlation code to the buffer register direct code or inversion. At each transmission, two bits are inverted; information and control. corresponding to the byte, which includes the inverted information (th bit, or one bit of the correlation code. The decoder 14 is designed to determine by the code of the discharge syndrome incorrectly read from memory block 22 to register 5 information. Decoder output

14 is fed to the input of block 3 of the element I. The decoder 15 is used to determine by the syndrome code the number of the byte in which the incorrectly read information bit is located. The output of the unit 14 and 15 receives the output of the comparison unit 10, on which the syndrome code is generated. The error register 16 serves to fix the occurrence of an uncorrectable error. When such a situation arises, to ensure the possibility of analyzing the reasons for the failure, the operation of the RAM, as well as devices with which it is {{a), must be suspended.

Methods for analyzing such situations can be very diverse: both manual and automatic, but for invention it is not of fundamental importance.

The element OR 17 generates the signaling of the suspend operation of the RAM and the matching of the 1..1x devices with it in the event of zero inequality of at least one register bit of 16 errors.

The syndrome analysis block 18 is used to recognize the correlation Mbix of the errors of the operative memory by the syndrome code. The functional block diagram 18 is shown in FIG. 2 and contains elements И OR 18.1, elements AND 18.2, 18.3 and 18.4, element OR 18.5.

The signal at the output of element 18.2 says that in the code of the syndrome, the discharge of a common parity is equal to one, and the remaining bits are not equal to a gimlet, that is, s. there is a correctable error. The signal at the output of element 18.3 indicates that the total parity in the code of the syndrome is equal to the bullet, and the remaining bits are not zero, i.e. there is a double error. The appearance of a signal at the output of element 18.4 indicates that a triple error has occurred or the bit of the total sharpness has been incorrect. Double and triple errors are not corrected by the device, with element 18.5 producing a sign of uncorrectable error.

Counter 19 sb (the phasing serves to pszdat the number of corrected errors. Oi contains eight bits, the highest bit is connected ne by the counting one, and the setting input. This bit indicates that the maximum value of the counter 19 is reached. In the zero state the high bit counter Fault 19 is set to n) and initial reset. Counter 9 is made on the triggers, it has indication outputs. The first output is a 72-wire line, the Fi of which 64 buses are used, E.1 transmission of information in eight test bits. The second output of the terminal is a single-wire line, through which the signal is suspended for work, a-i power and relative devices in the event of an uncorrectable.

The RAM unit 22 serves to store information and includes, in addition to zomnomoyunith mat, circuits, ip addresses, and usi circuits; 1 read and x bits of information. Register 23 serves to store the states of the uniform outputs of register 4 addresses. The control module 24 serves to memorize the zero outputs of the address register 4. Register 25 serves to record 1P1 state of direct outputs by comparing the block I). Register 26 is used for zagumin H1 states and 1-reverse outputs of block 10 comparison circuits. Registers 23--26 are set to 1: 1) on synchronous P triggers. Ying (} 10rmats on registers 23 --- 26 is entered in case of finding 11K-1 of a corrected error by signal from 11 bn; Yuki 18 a 1aliza syndrome. Trigger 27 sec. Tuzhit to memorize the unit output of the discharge, 11ri 1 that h ) and read1) from the current memory RAM, register 5 of the information is incorrect, and the trigger 28 stores the state of the zero output of the specified bit. Both triggers 27 and 28 are Ktriggers.

The selection block 29 serves to discharge a register of information incorrectly read from the memory block. From the outputs of block 29, the state of the left and the single outputs of the discharge are transmitted for memorization to the inputs of the flip-flops 27 and 28. The selection of the discharge is performed in accordance with the excited output bus of the digitizer 14. The selection unit 29 is constructed by selectors 500 LM 01.

The display unit 30 serves to indicate the location of the fault. In each specific case, this can be a bit number, an address, an address field indicating one of the coordinates. In addition, block 30 indicates the nature of the malfunction “Europe 1 unit,“ Bed unit. 1 on the inputs of the block 30 indication sv zar with registers 23-- 26 and triggers 27 and 28.

A functional diagram of one bit of the display unit is shown in FIG. 3. It contains And 30.1, 30.2 and 30.3 elements and display elements 30.4 and 30.5 (halogen lamp or LED). The display unit 30 operates as follows 1) m. E: If malfunctions occur when alarms occur, and the maximum bit of blocks 4, 10, and 5 are in different states, then there will be a setting that triggers to one state. It is also used in blocks 23-27 and in blocks 24, 26 and 28. In this case, output 30. I have a 3iipe signal and no indication element is turned on. Ns..ti also in the event of analysis failures, the discharge of blocks 4.10.5 iiaxd / uncH in one of some states P1i, roijia then; and, to one trigger it corresponds to) | tsgo razra yes blocks 23-28 is set to one state the This includes one of the indication elements 30.4, 30.5, and various colors.

Before the operation of the device during the period of routine maintenance, the blocks of the device 19, 23, 24, 25, 26, 27 and 28 along the circuit of the initial installation are reset to the initial zero state. In order not to unload the drawings with connections that do not have a principled value, the initial installation value is not shown.

The device has two modes of operation: “Write and“ Read. In the Recording mode, from the devices associated with the operational memory, the address register 4 receives the address to which the recording should be performed, the buffer register 6 receives information with control () ly) bits. The correctness of the address reception is monitored by the unit 11 of the convolutions modulo two, and the information by the unit 8 modulo two adders. If the information is received incorrectly on the indicated registers, blocks 11 and 8 generate error signals, which) insert the corresponding bits of the 16 error register into one unit and as a result the recording process is terminated. If no errors were detected, a correction code is generated by a block of 8 adders, but module two and the information together with the correction code are received into register 5 of the form 1i. When the “Record In (() Organization” Signal on the first input into the device together with the correction code is recorded, the Record is written to the memory block 22.

In the mode “Reading from the devices connected to the operational memory, the address to register 4 is entered into the address to which the address must be received. Then, at the first input I into the device, the sigpal “Read. As a result, the register 5 receives information from the kodo.m correction. Information bits from the third output of the information register are fed to the input of block 9 modulo-two adders. By the block 9, in accordance with the information received at its input, a correction code is generated on the first output, and control bits are generated on the second output.

The correction code from the second information register output (read) and the correction code from the first output of the second block 9 adders (formed) are compared in block 10 of the comparison. As a result, a code is generated at the output of the comparison unit. Received in block 18 analysis of the syndrome. If block 18 detects an uncorrectable error, a signal is generated at its output that establishes the corresponding register register of 16 errors per unit, which pauses the operation of the RAM and the associated devices. If the analyzing unit 18 is detected as synodable

aroma mistake. This state of the fault counter 19 is increased by one. The decoder 15 excites the entrance of the valve unit 13, which corresponds to the syndrome code, and through it information is transmitted to the buffer register 7 (information bits of the correction code). The decoder 15 excites the corresponding syndrome code 1. The input of the valve block 13 through which the check bits are transferred to the buffer register 1. At the same time, the bits of the register 4 addresses, the outputs of the comparison block 10, the distorted information of the register 5, are copied to the registers and the triggers of blocks 23–28. Then the corrected information is sent to the bu-footer, firs register 7, checked; it is received by the block 12 of the convolutions through the module and is transmitted to the devices contiguous with the RAM. In addition, with 6y (JiepHoro register 7, informational times |) and the bits of the correction code are transmitted to the register input) the regeneration interface.

Taking into account that the device works without interruption, the process of juicing the back of the back without affecting the patient mapiPugo time is ofiiiaOoTaTb significant number of failures. After the display of the special features of the 6CpoefiHR device, the display unit is infected with the state of the register fields, having a character for all the faults. For example, if a malfunction occurs on one of any bits}, then the number of the sbs digit will be displayed in the display module with the comparison unit, after processing all the faults. If HcnciipaniiocTii svzppa with a smpibka address transmission schemes or deshi schemes (| 1 address address, then, 11) 11 provided that the counter has 19 maximum failures, in b; 1ok (. The display will display the address, or one address coordinate .

The proposed device will allow you to locate 1 malfunctions of the RAM having a moving character and allow for the distortion of information in one bit,

parallel with solving tasks on a computer, without wasting time and without a significant increase in equipment.

The invention has become possible due to the possibility of processing the erroneous information, simultaneously with its fixation on additional regs) ah. without accumulation in buffer units). The most expedient use of this device is to troubleshoot a 2.5D RAM. AT

2.5D, some memory, built according to the scheme, and the same windings iso.i.zuyuts; both as address, and as dn d111e. lIovTo iy in a number of cases, the fault to the address you perceive is; K; IK acr dia. To ensure that the diagnosis is correct.

In this case, a large number of failures need to be handled (on the order of 00). The use of this device allows you to avoid errors in determining the location of the malfunction and thereby eliminate unproductive loss of time.

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Claims (1)

A MEMORY DEVICE WITH SELF-CONTROL, containing a memory block, the address input of which is connected to the first output of the address register, the information input of the memory block is connected to the first output of the information register and the first input of the block of elements AND, the output of the memory block is connected to the first input of the information register, the second input of which connected to the first output of the first adder unit modulo two, the third input of the information register is connected to the first input of the first adder unit modulo two and to the first output of the first buffer the register, the outputs of which are information inputs of the device, the second output of the first buffer register is connected to the second input of the first block of adders modulo two, the second output of which is connected to the first input of the error register, the second input of the error register is connected to the output of the first convolution block, 'the first and second the inputs of which are connected respectively to the second and third outputs of the address register, the second output of the information register is connected to the first input of the comparison unit, the second input of which is connected to the first output the second adder unit is modulo two, the input of the second adder unit is modulo, two is connected to the third output of the information register 1, the fourth input of which is connected to the first output of the second buffer register, the second output of the second adder unit modulo two is connected to the second input of the AND block, the third input of which is connected to the output of the first decoder, the first output of the comparison unit is connected to the input of the first decoder, to the input of the second decoder and to the input of the syndrome analysis unit, the first output of which is connected to the input at the counter, failures, the output of the second decoder is connected to the fourth input of the And block, the output of which is connected to the input of the second buffer register, the second output of the second buffer register is connected to the input of the second convolution unit and is the information output of the device, the second output of the syndrome analysis unit is connected <g to the third input of the error register, the fourth input of which is connected to the output of the second convolution unit, the output of the error register is connected to the input of the OR element, the output of which is the control output of the device, The odes of the first buffer register are information inputs of the device, characterized in that, in order to improve performance, it contains four registers, two triggers, a selection unit and an indication unit, the first and second inputs of which are connected to the outputs of the first and second triggers, respectively, the third input the display unit is connected to the output of the first register, the first input of which is connected to the first input of the second, third and fourth registers, to the first inputs of the first and second triggers and to the first output of the syndrome analysis unit ohms, the second inputs of the first and second triggers are connected to the corresponding outputs of the selection block, the first and second inputs of which are connected respectively to the output of the first decoder and to the first output of the information register, the fourth input of the display unit is connected to the output of the second register, the second input of which is connected to the third you i 0769.52 go the address register, the fifth input of the display unit is connected to the output of the fourth register, the second input of which is connected to the second output of the comparison unit, the sixth input of the comparison unit is connected to the output of the third register, the second input of which is connected to the third output of the comparison unit.