SU1037235A1 - Channel-to-channel adapter - Google Patents

Description

and two delay elements, the first and second inputs of the first element I are connected respectively to the outputs of the first elements NOT and the trigger, the output to the first input of the second trigger, the output connected to the first inputs of the first trigger and the second and third elements I, the output of which is connected to the first input of the third trigger, the second input and the output of the second element And are connected respectively to the output of the second element NOT and the first input of the fourth trigger, the output of which is connected to the input of the first delay element and the first input m of the fourth Element And, and the input with the second output of the simulator and the output of the fifth trigger, the first input of the fourth element And connected to the output of the fourth element And connected to the first input of the sixth trigger, the second input of which is connected. to the output of the first delay element, and the output to the second inputs of the third and fifth triggers and through the second delay element to the first inputs of the sixth and seventh And elements, the output of the sixth And element is connected to the second input of the second trigger, the third ;;; the output of the fourth trigger, and the fourth input to the output of the third trigger and the first input of the fifth element I, the second input of which is connected to the output of the third element NOT, the third and fourth inputs of the sixth trigger are connected respectively to the outputs of the second trigger the seventh element And the inputs of the first, second and third elements are NOT connected respectively to the second inputs of the first trigger, fourth and third elements And and the corresponding bus input simulator, the third inputs of the second and. third elements And the second inputs of the sixth and seventh elements And connected to the corresponding tires input simulator, the outputs of the first, third and fourth triggers are connected with the corresponding tires of the first output of the simulator.

3. The device according to claim 1, 1 and 2, wherein the control node comprises an input decoder, an output decoder, a clock generator, a state decoder, and a group of triggers, the first to fourth inputs of the input decoder are connected respectively to the first fourth inputs of the node, and the fifth input with the output of the state decoder and the first input of the output decoder, the group of outputs of which is connected to the first to sixth outputs of the node, and the second, third, fourth and fifth inputs respectively to the first, third and fourth inputs of the node, ne The first and second inputs of the group triggers are connected respectively to the first and second groups by the output of the input decoder, the third inputs are connected to the output of the clock signal generator, and the outputs are connected to the group of inputs of the state decoder.

The invention relates to computing and can be used in multi-machine computing complexes for interfacing digital computers.

Channel-to-channel adapters are known that contain a buffer register, two semi-adapters, a command comparison unit, and an L1 mode setting unit.

A disadvantage of the known adapters is low reliability and limited functionality, which leads to poor performance of the computing systems where they are used.

The closest in technical essence to the present invention is an adapter channel-channel containing a buffer register and two semi-adapters, each of which consists of input and output signal nodes, a command register connected by an output via a decoder of commands to the first input of the control node, and input the input node with the corresponding information input of the adapter, the address register, the output connected via the address comparison node with the second input of the control node, the third input and the first output of which are the control input and output of the adapter, and the second and third outputs are connected respectively to the first and second inputs of the output signals node, the third input of which is connected to the second input of the address comparison node and the output node of the input signals, the output to the corresponding information output of the adapter, and the fourth input is via the status register with the fourth output of the control node, the fifth output of the command register connected to the second input, and the sixth input to the third input of the node. address comparison, the output of the buffer register is connected to the fifth inputs of the output nodes of the semiadapters, the first and second inputs, respectively, to the outputs of the input nodes of the semiadapters, the third and the fourth inputs to the seventh 1m output node of the semiadapters, the third input and the eighth output of the first node the semi-adapter is connected respectively to the eighth output and the third input of the control unit to the second half of the adapter 2 J.  A disadvantage of the known adapter is low reliability, determined by the long adapter recovery time.  This is due to the fact that test and diagnostic testing programs of a known adapter must be placed in two.  DVRs that it matches.  These programs are complex and tightly coupled.  When testing, it is possible to connect the adapter to two channels of a single digital computer and (to PRODUCE diagnostics using the program of this digital computer.  In this case, however, the adapter test is associated with a mechanical switching of the connectors and, as a result, an increase in repair times.  In addition, when testing a known device, it is impossible to exactly.  but to determine the location of the malfunction, since the test program exchange command jointly executes not only two semi-adapters, but also two I / O channels. As a result, the need for long switching failures and low resolution of the diagnostic I programs result in a significant reduction in availability the main reliability parameter of multimachine complexes.  15.   The aim of the invention is to increase the reliability of the adapter.  The goal is achieved by the fact that the adapter contains a buffer register and two semi-adapters, each of which consists of. from the input amplification node, connected by the output to the first inputs of the command register and the address comparison node, the address register connected to the second output.  the input of the address comparison node, the control node whose first input is connected via a command decoder to the output of the command register, the second input to the output of the address comparison node, the first output to the second input of the command register, the second output directly, and the third output through the status byte register respectively, to the first and second inputs of the switching node of the output signals, the inputs of the gain nodes of the input signals of the first and second semi-adapters are connected respectively to the first and second information inputs of the adapter, and the outputs respectively -retarded with first and second inputs of the buffer register, the third and fourth inputs which are respectively connected to fourth outputs of the control units poluadapterov first and second, and third inputs Tide n outputs are connected respectively with the first and second by the control inputs and outputs. the adapter, the output of the buffer register is connected to the third inputs of the nodes that simulate the output signals of the first and second semi-adapters, the outputs of which are the first and second information outputs of the adapter, respectively, the fifth control inputs of the first and second semi-adapters, respectively, the first and second control outputs of the adapter , i, a half-adapter simulator and three multiplexers are introduced, with the output of the address register in each half-adapter connected to the fourth input of the output switching node, the outputs of the first second, third and third multiplexers are connected respectively to the fourth inputs of the control nodes — the first and second semi-adapters and the input of the semi-adapter simulator, and the first and second inputs — respectively to the outputs of the decoder commands of the first and second subadapters; the sixth outputs of the control nodes of the first and second semi-adapters are connected respectively to the third and fourth inputs are one third of its multiplexer and to the third inputs of the second and first multiplexers, the fourth inputs of which are connected to the first output of the simulator by of the luadapter, the second output of the buffer register connected to the fifth input, and also the fact that the simulator of the semi-adapter contains six triggers.  Three elements are NOT, seven elements are AND, and two delay elements, the first and second inputs of the first element And are connected respectively to the outputs of the first elements NOT and the trigger, the output to the first input of the second trigger, the output connected to the first inputs of the first trigger, and the second and The third And elements, the output of which is connected to the first tertiiero trigger input, the second input and the output of the second element And are connected respectively to the output of the second element NOT and the first input of the fourth trigger, the output of which is connected to the input of the first el the delay element with the first input of the fourth element is And, and the input with the second output of the simulator and the output of the fifth trigger, the first input connected to the output of the true element And, the output of the fifth element AND is connected to the first input of the sixth trigger, the second input of which connected to the output of the first delay element, and the output to the second inputs of the third and fifth triggers and through the second delay element to the first inputs of the sixth and seventh elements And, the output of the sixth element is connected to the second input of the second trigger, the third input of the connected to the output of the fourth trigger, and the fourth input to the output of the third trigger and the first input of the fifth element I, the second input of which is connected to the output of the third element H, the third and fourth inputs of the sixth trigger are connected respectively to the outputs of the second trigger and the seventh element And, inputs the first, second and third elements are NOT connected respectively. with the second inputs of the first trigger, the fourth and third of its elements AND, and the corresponding input tires of the simulator, the third inputs of the second and third elements AND, and the second inputs of the sixth and seventh I elements are connected to the corresponding inputs of the simulator, the outputs of the first, third, and fourth triggers are connected with the corresponding buses of the first output of the simulator, and the fact that the control node contains an input decoder, an output decoder, a clock generator, a decoder of states, and a group of triggers, the first to fourth inputs the input decoder is connected respectively to the first to fourth inputs of the node, and the fifth input is connected to the output of the state decoder and the first input of the output decoder, the output group of which is connected to the first to sixth outputs of the node, and the second, third, fourth, and fifth inputs are respectively with the first, third and fourth inputs of the node, the first and second inputs of group triggers are connected respectively to the first and second groups of outputs of the input decoder, the third inputs are connected to the output of the sync signal generator, and outputs to the group of inputs of the decoder states  FIG.  1 is a block diagram of an adapter; in fig.  2 and 3 are examples of functional diagrams of the control node and simulator of the semi-adapter.  The adapter contains (FIG.  1) semi-adapter 1 and 2, each of which consists of a node 3 amplifying input signals, a register of 4 commands, a decoder of 5 commands, a register of 6 addresses, a node of 7 address comparison, a control node-8, an output switching node 9, and a register of 10 bytes nor, buffer register 11, multiplexers 12th and simulator 15 semi-adapters.  FIG.  1 shows bus lines 16-21 of semi-adapters 1 and 2 with multiplexers 12-I, buses of outputs and input of simulator 15 semi-adapters, as well as buses 25 and 2b of information inputs of the adapter, buses 27 and 28 of the control inputs of the adapter, tires 29 and 30 of the adapters adapter outputs and bus 31 and 32 adapter information outputs.  The control unit 8 comprises (FIG. 2) an input decoder 33, a generator of 3 clock signals, a group trigger, a decoder of 0 states, and an output decoder k.  The simulator 15 semi-adapter contains (FIG.  H) triggers 42-27, elements NOT 48-50, elements And and elements 5B and 59 of the delay.  Adapter channel-channel works as follows.  A channel (for example, the first channel connected to semi-adapter 1) performs an initial adapter sample. The address from the first channel on bus 25 through node 3 enters node 7, which is compared with the address of the semi-adapter assigned to it in the system and stored in address register 6.  Register 6 can be made in the form of a toggle register.  The result of the address comparison (the Address coincidence signal) is output to node 8, which, depending on the control signals of the first channel on bus 27 and the signals from the outputs of decoder 5i of node 7 and multiplexer 12, produces signals that ensure the operation of the adapter in accordance with. OST k GO 30i. 000 EU I / O interface computer.  If the addresses match, then from register 6, the adapter's return address is output through node 9 to information buses 31 and then to the first channel, which compares the address received from the adapter with the address previously provided to buses 25 and, if they match, issues a code to buses 25 command exchanges, which is stored in register k and decoded by decoder 5.  In the command code the decrees „- -. . x  hch |. . , ":.  , , i is the adapter operation mode (Operation or Control).  The signals from the output of the driver 5 are fed to the inputs of node 8 and multiplexers 12-14, and determine the mode of operation of the adapter.  In the Operation mode, information is transmitted between the channels with the participation of two pounds 1terov 1 and 2.  In this connection. between semi-adapters 1 and 2 is carried out through multiplexers 12 and 13, the passage of signals through multiplexer 14 is prohibited and the simulator 15 does not work.  In the Control mode, a full autonomy is performed (without the fate of the adjacent semi-adapter and the channel connected to it) checking the half-ter of 1ter.  During testing of the semi-adapter 1 using multiplexers 12 and 14, communication is established between the semi-adapter 1 and the simulator 15.  During the test of the semi-adapter 2, the simulator is connected using multiplexers 13 and 14.  In the Operation mode, after deciphering the command of the first channel requiring the corresponding command of the second channel, semiadapter 1 places the command.  to the buffer register 11 and generates a signal 1 5,8 waiting for approval (Waiting, matching), which the multiplexer 13 enters into the semi-adapter 2.  (Coordination is required by commands associated with transferring data from one channel to another.  A write command from one channel corresponds to a read command from another channel and vice versa.  Semi-adapter 2 issues status bytes to the second channel with an Attention pointer, in response to which the second channel sends a state clarification command to the adapter.  At this command, the semi-adapter 2 transmits the contents of the buffer register 11 to the second channel, and so on. e.  command sent by the first channel.  The programmatic computer, to which the second channel is connected, determines which matching command should be sent to the adapter and then sends this command.  If the commands are matched, the semi-adapter 2 sends an approval confirmation signal (Confirmation confirmation) to the node 8 of semi-adapter 1, after which both semi-adapters execute the exchange instructions together before completion.  In this case, the information byte received, for example, from the first recording channel, is placed in the buffer register 11, after which a ready signal (Ready) is sent to the semi-adapter 2, via which the semi-adapter transmits this information byte to the second channel and sends the semi-adapter 1 signal to confirm the transfer of information (Confirmation of readiness).  During the exchange process, a status byte is generated in register 10, which is transmitted to the channel during the initial sampling and after the exchange is completed.  Node 8 can be implemented in the form of a synchronous "| and (new machine.  The state of node 8 is determined by the states of the flip-flops 35-39, which change their states on the front of the clock pulses produced by the generator 34.  Depending on the input signals of the node 8 and the previous state of the node 8, the ROSCOM decoder 33 generates control signals at the inputs of the triggers 35-39, which determine the following states of the node d.  At the output of the decoder 40, a signal / m 1 is generated corresponding to the state of the flip-flops 35-39.  The output decoder 41, depending on the state of the node 8 and the input signals, generates the external control signals of the node 8.  The control buses of channel 27 (28) to the input of the decoder 33 receive control signals of the channel - ADR-K, UPR-K, VBR-K, INF-K, BLK-K, RVB-K, RAB-K according to the input-output interface .  The decoder receives the signals Write, Read, Refine, Immediately perform an operation (for example, Check I / O or Idle), Work generated by decoding the exchange command.  The tires 20 (21) in the Work mode receive signals from the output of the adjacent semi-adapter, and in the Control mode - signals from the simulator 15 semi-adapter.  The Waiting for Negotiation signal is generated by the adjacent Noad Adapter when it receives a command that requires matching.  On this signal, node 8 generates signals that provide a status byte with a pointer to the channel.  The Ready signal is produced by an adjacent semi-adapter and an IM 15 after the data byte for transmission is written to the buffer register 11.  The Write and Read signals are generated by the adjacent semi-adapter, determine the type of command to be executed, and are used to determine the correspondence of the commands received.  The Signal Confirmation Signal is generated by an adjacent semi-adapter and simulator 15 in response to a signal Waiting for Negotiation after receiving a negotiated command - The End Signal is generated by an adjacent semi-adapter after the channel associated with it has issued an ending sequence.  The readiness confirmation signal is generated in response to the Ready signal after the byte from buffer register 11 is transmitted to the channel, the signals from the second output of the node enter the input of node 9 and are controlled by switching or information from the buffer register 11 or byte from the register 10, or addresses from the register 6 - to tires 31 - (32).  On tires 29 (30), signals are generated for the control of the TRB-A, ADR-A, VBV-A, UPR-A, INF-A, RAB-A subscribers.  The signals from the third of its output from the control node are fed to the input of register 10, where according to them, the following bits of the status byte are deduced.  On a signal 35 on the first and fourth exits of a node.  8, information is recorded in registers and 11, respectively.  The signals from the sixth output of node 8 are fed to the inputs of multiplexers 13 and k, and then, in the operating mode, to the input of the adjacent semi-adapter, and in the mode. Control - at the input of the simulator 15.  In Control mode, a command received from the channel is not placed in the buffer register.  In this mode, the internal interface signals of a semi-adapter adjacent to the one being tested (Confirmation confirmation, Confirmation of readiness, Ready) are produced by the simulator 15.  To check the semi-adapter, a channel (for example, the first channel when checking semi-adapter 1) sends a write command, in the code of which the indication of execution of the command in the Monitoring mode is set.  The signal from the output of the decoder 5 connects the simulator 15 through multiplexers 12 and 1 to the first semi-adapter.  Each byte of information received from the channel, in the course of the write operation, is entered into the buffer register 11.  After the write operation is completed, the channel sends a read command to the checked semi-adapter, which, when executed, transfers information from the buffer register 11 to the channel.  The first byte contains the information transmitted in the last byte when performing a write operation.  The value of the information in each subsequent byte is increased by + V compared to the previous one.  The addition of +1 to the contents of register 11 is effected by the signal at the second output of the simulator 15, which arrives at the counting input of the buffer register 11.  The end of the exchange is made in the control mode initiated by the channel.  The simulator of the semi-adapter 15 is a digital automaton, the states of which are determined by the states of the flip-flops.  In the Control mode, the input of the simulator 15 receives signals of the tested semi-adapter: Waiting for approval, Ready, Confirmation of readiness.  Read, Write, Finish, at the output of the simulator 15 signals are generated Confirmation of readiness, Confirmation of approval, Ready, indicating the work of the semi-adapter adjacent to the checked one.  After receiving a command that requires matching, the tested semi-adapter issues a Waiting for Matching signal, according to which the trigger 42 is set to state 1, which corresponds to the second state of node 8.  Signal Confirmation confirmation from the output of flip-flop Q2 enters the checked semi-adapter, which resets the Waiting for Compatibility signal and goes to the data transfer cycle.  By resetting the signal Waiting for consistency, the ijS trigger is set, and then the trigger t2 is reset.  Node 8 enters the third state.  Further, depending on the command executed by the second half-adapter (Write or Read), the following are performed. action  When the write command is executed, the checked semi-adapter receives the data beit from the channel, writes it to the buffer register 11, and issues a Ready signal, indicating that the information in the buffer register is ready.  On the Record and Ready signals, the trigger is set and then the HS / C: reset trigger (node 8 goes to the fourth state).  The signal Confirmation of readiness from the output of the trigger t enters the checked semi-adapter, informing the latter that the information from register 11 is read and can be written to it. new information.  On a signal to confirm the readiness of the checked semi-adapter turns to the channel, following the next data byte.  The channel either transmits a data byte (in this case, the signal Terminate 0), or responds with the sequence of the end of the exchange operation (in case of completion of the transfer of the data array specified in the exchange command).  In the latter case, verifiable to the floor.  The adapter issues a finish signal.  After the transition from the seventh state to the first or third state, the tested semi-adapter resets the signal of Com.  This sets trigger 7 and flushes trigger k.  The node 8 enters the seventh state, the duration of which is determined by the delay time of the element 59.  Then the node B goes to the third state or to the initial state.  If the checked semiadapter performs the Read command, then from the third state the automaton goes to the fifth state (by the Read and Read Ready signals, the trigger 5 is set, after which the trigger is reset).  Signal Ready from trigger output 45. post. It goes to the checked semi-adapter, signaling the readiness of information in the buffer register.  By this signal, the checked semi-adapter transmits information from buffer register 11 to the channel.  The channel either accepts a data byte, or responds with a sequence of exchanges (semi-adaptive P generates a terminate signal), after which the semi-adapter issues a Confirmation of Readiness signal, on which the trigger 46 is set and the trigger 45 is reset.  The signal Adding -fl from the output of flip-flop 46 is fed to ho bus 22 to the counting input of the buffer register 11, where one is added to the contents of the buffer register.  Signal duration Adding h − 1 is determined by the delay time of element 58.  After this. time node 8 enters the seventh state.  The transition from the seventh state to the third or to the first state is described above.  Thus, in the proposed adapter, the possibility of autonomous testing of each semi-adapter is provided, which allows to increase the resolution in the diagnosis of malfunctions and shorten the time for troubleshooting.

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Claims (3)

1. CHANNEL-CHANNEL ADAPTER, containing a buffer register and two half-adapters, each of which consists of an input signal amplification node connected by an output to the first inputs of the command register, and an address comparison node, an address register connected by an Output to the second input of an address comparison node, node control, whose first input is connected via the instruction decoder to the output of the instruction register, the second input - to the address comparison unit outputs, a first output m to the second input of the instruction register, the second output directly and the third You are a _(run through the registers of status byte, respectively, to the first and second inputs of the output signal switching node, the inputs of the amplification nodes of the input signals of the first and second half adapters are connected respectively to the first and second information inputs of the adapter, and the outputs are respectively with the first and second inputs of the buffer register, the third and fourth inputs of which are connected respectively, to the fourth outputs of the control nodes of the first and second half-adapters, the third inputs and fifth outputs of which are connected respectively to the first and second control the inputs and outputs of the adapter, the output of the buffer register is connected to the third inputs of the nodes, switching nodes of the output signals of the first and second half adapters, the outputs of which are the first and second information outputs of the adapter, the fifth outputs of the control nodes of the first and second half adapters are the first and second control outputs, respectively adapter, characterized in that, in order to increase the reliability of the adapter, a simulator of a half-adapter and three multiplexers are introduced into it, and the output of the address register in each luadapter is connected to the fourth input of the switching node 'output signals, the outputs of the first, second and third multiplexers are connected respectively to the fourth inputs of the control nodes of the first and second half-adapters and the input of the imitator of the half-adapter, and the first and second inputs, respectively, to the outputs of the decoders of the first and second half adapters, the sixth outputs of the control nodes of the first and second half adapters' are connected respectively · to the third and fourth inputs of the third multiplexer and to the third in-. * I will give the second and first multiplexers, the fourth inputs of which are connected to | the first output of the half-adapter simulator, the second output connected to the fifth input of the buffer register. 2. The device according to π. 1, the fact that the semi-adapter simulator contains six triggers, three NOT elements, seven AND elements SU „Л037235 and two delay elements, the first and second inputs of the first element And connected respectively to the outputs of the first elements NOT and the trigger, the output to the first input of the second trigger, the output connected to the first inputs of the first trigger and the second and third elements And, the output of which connected to the first input of the third trigger, the second input and output of the second element AND are connected respectively to the output of the second element ^ NOT and the first input of the fourth trigger, the output of which is connected to the input of the first delay element and to the first input the fourth element AND, and the input with the second output of the simulator and the output of the fifth trigger, the first input connected to the output of the fourth element And, the output of the fifth element And is connected to the first input of the sixth trigger, the second input of which is connected. to the output of the first delay element, and the output to the second inputs of the third and fifth triggers and through the second delay element to the first inputs of the sixth and seventh elements AND, the output of the sixth element And is connected to the second input of the second trigger, the third leaving connected to the output of the fourth trigger, and the fourth input - to the output of the third trigger and the first input of the fifth element AND, the second input of which is connected to the output of the third element NOT, the third and fourth ”inputs of the sixth trigger are connected respectively to the outputs of the second trigger and of the seventh element And, the inputs of the first, second and third elements are NOT connected respectively to the second inputs of the first trigger, the fourth and third elements And and the corresponding input bus lines of the simulator, the third inputs of the second and third elements And and the second inputs of the sixth and seventh elements And are connected to the corresponding to the input buses of the simulator, the outputs of the first, third and fourth triggers are connected to the corresponding buses of the first output of the simulator. 3. The device pop. 1, wherein the control unit comprises an input decoder, an output decoder, a clock generator, a state decoder and a group of triggers, the first and fourth inputs of the decoder being connected respectively to the first fourth inputs of the node, and the fifth input to the output of the state decoder and the first input of the output decoder, the group of outputs of which is connected to the first to sixth outputs of the node, and the second, third, fourth and fifth inputs, respectively, with the first, third and fourth inputs of the node, the first and second inputs the riggers of the group are connected respectively to the first and second groups by the output of the input decoder, the third inputs to the output of the clock generator, and the outputs to the group of inputs of the state decoder.